6006186fe0
phy/rmii: use 50MHz (instead of 100Mhz) and use DDROutput to generate ref_clk
2015-12-03 23:47:08 +01:00
09e6b3a8d7
phy: add s7rgmii
2015-12-01 01:34:06 +01:00
6b39b0f674
phy: fix clock domains renaming (ClockDomainsRenamer refactoring issue)
2015-11-30 13:04:47 +01:00
133cb88ead
common: small cleanup
2015-11-27 19:51:26 +01:00
449d84bf11
remove Counter module
2015-11-24 21:02:07 +01:00
9a7039ef72
use mininal imports
2015-11-24 20:44:00 +01:00
09dad1b520
phy/rmii: adapt to new syntax and fixes
2015-11-19 15:42:51 +01:00
f1725d5fd1
ethetbone software is now integrated in LiteX
2015-11-17 12:04:04 +01:00
155be56f9c
test: use new RemoteClient/RemoveServer provided by LiteX
2015-11-17 00:21:08 +01:00
34b6994d3c
stream/SyncFIFO now exposes fifo level
2015-11-16 16:12:41 +01:00
94e5c254eb
fix some imports
2015-11-14 20:17:47 +01:00
fda5ea0522
update setup.py
2015-11-14 17:28:40 +01:00
c1d7f2d427
phy: rename sim to model and remove from autodetect
2015-11-14 03:43:27 +01:00
88e18dfa23
doc: remove skeleton and change logo (we'll add a better doc later)
2015-11-14 00:58:43 +01:00
e7caf8acfb
use stream_packet and stream_sim from litex
2015-11-14 00:42:33 +01:00
b370c8b2f5
use stream_packet and stream_sim from litex
2015-11-14 00:35:38 +01:00
3f9e4d7882
README: update
2015-11-13 23:51:23 +01:00
d84d610104
simulations working with litex and vpi
2015-11-13 15:11:57 +01:00
7b9dc92b0b
for now use our fork of migen
2015-11-13 14:48:53 +01:00
886108eee9
test: for now revert all simulation (we'll switch when missing feature of new simulator will be implemted)
2015-11-13 14:47:57 +01:00
57b70c640c
start adapting simulations to new migen (still some issues with Migen simulator)
...
Simulator issues:
- MultiReg not simulated correctly (I've used direct instantiation of MultiRegImpl to get simulation working)
- MemoryArray with granularity != 1 raise NotImplementedError
2015-11-13 13:46:05 +01:00
a032168997
start adapting to new migen/litex
2015-11-12 19:52:59 +01:00
0981ccfece
use our own migen/misoc fork for now since migen/misoc is evolving
2015-11-04 10:09:09 +01:00
e2292d17f8
phy/gmii: enable use of gmii phy on non Xilinx devices
2015-10-25 10:57:44 +01:00
9635a94769
README: cleanup
2015-10-24 14:03:43 +02:00
2b6dfa6a7e
cleanup (remove use of FlipFlop)
2015-10-24 13:28:09 +02:00
8514b9344d
README: update
2015-10-24 12:56:14 +02:00
56773f962f
identify some ressources optimization in HW icmp and etherbone
2015-10-24 12:55:49 +02:00
a6415c08b4
liteeth/phy/mii: use same code than liteeth_mini
2015-10-23 20:15:03 +02:00
57b671692d
core/ip: use decorators on LiteEthIPV4Checksum (cleanup)
2015-10-21 23:39:42 +02:00
7321e87cbb
phy: add RMII phy (not yet tested) assuming 100MHz cd_eth ClockDomain provided externally
2015-10-15 21:20:55 +02:00
e33937f089
move etherbone packets and record description to software
2015-10-13 21:36:37 +02:00
e61c229bbb
simplify organization (try to regroup layers in single files)
2015-10-02 10:38:43 +02:00
b4c3223a24
update litescope and build Devel targets in test
2015-09-27 19:17:07 +02:00
2b84ec066a
software: add uip (contiki) port (tested on lm32 and mor1kx)
2015-09-14 21:41:05 +02:00
0688532619
software: add lwip port (tested on lm32 and mor1kx)
2015-09-14 21:38:46 +02:00
d786380cd2
fix simulations (adapt to new organization) and and all target in Makefile to for regression testing
2015-09-12 20:53:14 +02:00
1d9ea484e2
test/Makefile: add example_designs to test regression on example_designs (only generate hdl)
2015-09-12 16:28:09 +02:00
58d45c873a
liteeth/common: add reverse_bytes, FlipFlop, Counter (will be removed from migen)
2015-09-12 16:27:07 +02:00
c8545ae06e
fix litescope import
2015-09-09 08:26:51 +02:00
306162096b
fix imports
2015-09-08 09:55:43 +02:00
23161d3a7d
add setup.py
2015-09-08 01:43:09 +02:00
20fc519410
init repo
2015-09-07 13:29:34 +02:00
Florent Kermarrec