ae10eea860
gen: add lattice support
2020-02-08 16:33:03 +01:00
081bf46ca6
mac/sram: simplify code and improve SRAM read speed using async_read on Memory.
2020-02-07 11:40:14 +01:00
bf4a11ab30
mac/sram: simplify counter (use NextValue in FSM)
2020-02-07 10:57:25 +01:00
721238b7a8
mac/sram: cosmetic changes
2020-02-07 10:53:05 +01:00
f532a12b40
phy/common: use CSRField for MDIO registers
2020-01-28 10:43:33 +01:00
8edf4f3f9a
phy/1000basex: cleanup primitive instances, use Open signal class on open ports, polish code comments
2020-01-28 10:43:08 +01:00
de40a66873
phy/gmii: cleanup BUFGMUX instance
2020-01-28 10:41:53 +01:00
983017a9ed
phy/rgmii: cleanup primitive instances
2020-01-28 10:41:32 +01:00
8a4f38339a
Merge pull request #28 from jersey99/phy-usrgmii
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Changes to get usrgmii and s7rgmii working in hardware
2020-01-28 08:54:09 +01:00
8ecaaf0546
phy/{s7,us}rgmii.py:
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Recent modification that adds S7PLL that in return adds an AsyncResetSynchronizer inside XilinxClocking.
This actually creates a multi-driven net because there is another AsyncResetSync* being added in the Phys.
This change instantiates the PLL without a reset for now, leaving the CD reset intact.
2020-01-27 12:52:10 -08:00
cd413c5c20
phy/usrgmii.py:
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IDELAYE3 requires EN_VTC to be enabled for fixed mode time delay. This eliminates implementation time CRITICAL WARNINGs and ensures generating a bitfile.
2020-01-27 10:32:38 -08:00
3a54bf2b8b
phy/rgmiis: uniformize a bit more
2020-01-18 00:24:40 +01:00
e41f06bbf2
phy: cleanup imports/dw
2020-01-17 23:19:56 +01:00
a48c78044e
phy/s7rgmii/usrgmii: use S7PLL and USPLL
2020-01-17 23:08:38 +01:00
1dab80dd30
Merge pull request #26 from jersey99/marblemini
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A few minor changes that help RGMII phy related debugging. {s6, s7, u…
2020-01-17 22:46:09 +01:00
c16e6b2d86
phy/ecp5rgmii.py: Missed moving dw as class variable here
2020-01-17 12:45:37 -08:00
0a922bb2ad
A few minor changes that help RGMII phy related debugging. {s6, s7, us}rgmii.py Make dw a class variable instead
2020-01-17 09:23:03 -08:00
17e228d4b0
phy/usrgmii: add configurable tx/rx_delay (2ns by default)
2020-01-17 09:24:35 +01:00
6270eb38d2
phy/s7rgmii: cleanup
2020-01-17 09:22:30 +01:00
ee4f8c0f34
phy/usrgmii: improve presentation
2020-01-17 09:15:51 +01:00
2bdae4e7bd
phy/s7rgmii: add configurable tx/rx_delay (2ns by default)
2020-01-17 09:13:29 +01:00
aea81e19e9
phy/s7rgmii: improve presentation
2020-01-17 09:05:09 +01:00
2748e442a9
phy/s6rgmii: add configurable tx/rx_delay (2ns by default)
2020-01-17 09:03:34 +01:00
8fb0dae18a
phy/s6rgmii: improve presentation
2020-01-17 08:57:52 +01:00
0cf9c2057d
phy/ecp5rgmii: add configurable tx/rx_delay (2ns by default)
2020-01-17 08:54:31 +01:00
e5c4ee7065
phy/ecp5rgmii: improve presentation
2020-01-17 08:35:15 +01:00
73bd27b506
phy/s7rgmii: add 2ns delay on ctl/data
2020-01-16 15:46:13 +01:00
f2b3f7eeb1
test: update test_etherbone, use litex.gen.sim for all tests
2019-11-25 11:43:16 +01:00
c71e42972a
test: add test_examples (and remove test/Makefile)
2019-11-25 09:35:16 +01:00
10a911088c
test: rename test_liteeth_gen to test_gen and call gen.py instead of liteeth_gen
2019-11-25 08:53:40 +01:00
6cce8c3c34
test: add test_liteeth_gen
2019-11-24 11:23:13 +01:00
bb01840b12
add initial LiteEth standalone core generator from examples/core.py
2019-11-24 11:22:51 +01:00
c1783ce554
examples/targets: update and cleanup
2019-11-23 19:49:23 +01:00
d3b2f3d361
examples/targets: udpate analyzer
2019-11-23 15:47:42 +01:00
dc8ddf6895
examples: keep up to date with LiteX
2019-11-23 15:23:24 +01:00
91f0f4ce80
test/model: improve presentation/readability
2019-11-23 15:17:22 +01:00
36c9951235
test: regroup model tests in test_model and run it with Travis-CI
2019-11-23 14:55:55 +01:00
7f31186b8c
add Travis-CI
2019-11-23 00:16:01 +01:00
bd1ead88d1
test: update for ci, for now disable test_etherbone since does not seem to finish
2019-11-23 00:14:19 +01:00
5a789570be
mac/wishbone: remove FullMemoryWE (prevent simulation and should no longer be useful)
2019-11-23 00:12:46 +01:00
57be29e68a
global: pass data_width(dw) parameter to modules to prepare for 10Gbps/25Gbps links
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To support 10Gbps/25Gbps, the hardware stack will need to handle multiple bytes/clock cycle.
Pass dw to all modules to allow making use of it in the future. For now dw=8.
2019-11-21 11:01:55 +01:00
ba83253ffa
core/arp: fix typo
2019-11-21 11:01:53 +01:00
6b0a9251c0
global: keep up to date with LiteX (update stream_packet import to packet)
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Retro-compatibily was ensure by LiteX but update it.
2019-11-21 11:01:50 +01:00
5bf218a00b
Merge pull request #23 from enjoy-digital/versa_ecp5_udp_loopback
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Versa ecp5 udp loopback example
2019-11-20 09:44:15 +01:00
e980b603cc
example/udp_loopback: simplify/cleanup and make it more generic
2019-11-20 08:53:16 +01:00
50cc7d0671
examples: add practical UDP loopback example with Versa ECP5
2019-11-20 08:18:50 +01:00
d2eb870445
core: allow passing ip_address as str
2019-11-07 13:23:10 +01:00
4d9e74f10a
phy/usrgmii: cleanup (style, indent)
2019-09-28 22:16:07 +02:00
4bc79cefd8
examples/targets/core: update
2019-09-24 12:53:06 +02:00
cd0eaa9607
Merge pull request #19 from jersey99/master
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Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940
2019-09-05 11:07:59 +02:00
Stefan Schrijvers
Florent Kermarrec
Vamsi K Vytla
Vamsi K Vytla
Yehowshua Immanuel