Florent Kermarrec
617400fe9e
test/test_etherbone: disable for now (hanging).
2020-12-17 19:06:11 +01:00
Florent Kermarrec
e270956d2d
test/test_model: fix test_etherbone.
2020-12-17 18:37:47 +01:00
Florent Kermarrec
d901027e5c
bench/test_etherbone/speed_test: use burst_size of 255.
2020-11-26 11:36:12 +01:00
Florent Kermarrec
d3788cd2bb
frontend/etherbone: use new LiteX's PacketFIFO in LiteEthEtherboneRecordSender.
...
This ensures the full Etherbone packet is available before starting the transmission
and fixes transmission issues with larges bursts or slow sys_clk_freq.
2020-11-26 11:35:51 +01:00
Florent Kermarrec
d3ae361748
bench/sim: fix sim ethernet tap ip address.
2020-11-26 11:29:50 +01:00
Florent Kermarrec
3afd62e2e9
bench: add sim (with similar features than hardware targets).
2020-11-25 19:45:22 +01:00
Florent Kermarrec
faf78965dd
bench/test_etherbone: allow direct CommUDP use with --udp.
...
Useful to compare performance with RemoteClient and CommUDP.
2020-11-25 15:15:08 +01:00
Florent Kermarrec
5abf44d89a
bench/targets: set buffer_depth to 255 (max).
2020-11-25 15:13:55 +01:00
Florent Kermarrec
c3e1dad289
bench: reduce buffer_depth/burst_size to 128 (maximum supported by Etherbone protocol is 255).
2020-11-25 09:13:23 +01:00
Florent Kermarrec
f97f6b0635
bench/test_etherbone/test_speeed: use bursts.
2020-11-24 19:46:43 +01:00
Florent Kermarrec
d1571ad1df
software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default).
2020-11-24 19:40:18 +01:00
Florent Kermarrec
5737aaa67c
ci: migrate from Travis-CI to Github Actions.
2020-11-24 13:36:06 +01:00
Florent Kermarrec
b1fd3e8092
bench/targets: increase buffer_depth to 256.
2020-11-24 10:19:52 +01:00
Florent Kermarrec
ca4284f977
bench: add colorlight_5a_75b test target.
2020-11-24 10:19:23 +01:00
Florent Kermarrec
c6cfed6294
frontend/etherbone: expose buffer_depth to user.
2020-11-23 17:44:47 +01:00
Florent Kermarrec
47100c5c4e
bench/test_etherbone: add initial speed_test.
2020-11-23 17:36:54 +01:00
Florent Kermarrec
3645d2f85f
bench: add initial test_etherbone.
2020-11-23 17:11:52 +01:00
Florent Kermarrec
c7d7561a38
bench/targets: add identifier and SRAM.
2020-11-23 17:11:36 +01:00
Florent Kermarrec
291b257eb4
phy/crg: make rst_n optional on all PHYs and minor cleanup.
2020-11-23 16:24:44 +01:00
enjoy-digital
75495dd6ec
Merge pull request #54 from rprinz08/master
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Fix syntax and load error in Wireshark etherbone dissector
2020-11-23 13:44:57 +01:00
Florent Kermarrec
41b0f0c774
add initial bench directory with minimal arty/genesys2 test targets.
2020-11-23 13:40:54 +01:00
Florent Kermarrec
53057121e7
examples: remove old examples and update README (new benches/examples will be added).
2020-11-23 12:54:09 +01:00
Florent Kermarrec
5247a2008a
phy/ecp5rgmii: remove p_DEL_MODE (not required since we specify DEL_VALUE).
2020-11-23 12:16:07 +01:00
rprinz08
d3bbd506ba
Fix syntax and load error in Wireshark etherbone dissector
2020-11-07 10:55:21 +01:00
Florent Kermarrec
06242564f7
frontend/etherbone: simplify LiteEthEtherboneRecordReceiver.
2020-11-06 19:49:07 +01:00
Florent Kermarrec
d96fdfc5e5
frontend/etherbone: simplify LiteEthEtherboneRecordSender using combinatorial logic and fix #52 .
2020-11-06 19:43:57 +01:00
enjoy-digital
0c287d07f8
Merge pull request #51 from gregdavill/ecp5rgmii_delay_fix
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phy/ecp5rgmii: Fix io delay blocks
2020-10-12 09:17:02 +02:00
enjoy-digital
7fa06adf78
Merge pull request #48 from kbeckmann/fix_test
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test_etherbone: Fix import of etherbone module
2020-10-12 09:05:05 +02:00
enjoy-digital
317154f68f
Merge pull request #49 from gregdavill/ecp5_timing_fix
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mac/core: Improve timing closure of core
2020-10-12 09:04:34 +02:00
Greg Davill
6ee11edb87
phy/ecp5rgmii: Fix io delay blocks
...
For correct io delays in nextpnr the DEL_VALUE parameter needs to
be an integer, instead of the "DELAY{}" string.
The use of a "DELAY{}" string appears in the Lattice primitive
manual, but appears to be incorrect. At least based of the current
nextpnr.
Because we are not making use of dynamic io delays here we can
also use the simpler DELAYG block instead of DELAYF.
Fixes #50
2020-10-11 15:16:58 +10:30
Greg Davill
9aee36939f
mac/core: Improve timing closure of core
...
On ECP5 targets the core struggles to meet timing closure. This
change adds buffers to the CRC module on tx/rx paths.
This results in 20-30MHz gain to max clock rate.
This fixes #47
2020-10-11 14:46:16 +10:30
Konrad Beckmann
054eebc25f
test_etherbone: Fix import of etherbone module
2020-09-30 21:04:11 +02:00
Florent Kermarrec
54acf9fd76
phy/pcs_1000basex: keep up to date with MiSoC (adds SGMII and 10/100Mbps support).
...
3768f5acc1
2020-08-24 22:14:35 +02:00
Florent Kermarrec
64b85e621e
add SPDX License identifier to header and specify file is part or LiteEth.
...
Artix7/Ultrascale 1000BaseX is reused from MiSoC/LiteEthMini, specify it.
2020-08-23 16:07:12 +02:00
Florent Kermarrec
f275af8297
liteeth_gen: get Wishbone Platform's IOs with Interface.get_ios.
2020-08-22 21:22:02 +02:00
enjoy-digital
0705b35399
Merge pull request #46 from Xiretza/gen-py-wishbone
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Update gen.py to work with latest LiteX in wishbone mode
2020-08-22 21:16:22 +02:00
Xiretza
6a9a5132f6
Update gen.py to work with latest LiteX in wishbone mode
...
Previously, it would fail with:
$ liteeth/gen.py examples/wishbone_mii.yml
[snip]
Traceback (most recent call last):
File "liteeth/gen.py", line 346, in <module>
main()
File "liteeth/gen.py", line 331, in main
soc = MACCore(platform, core_config)
File "liteeth/gen.py", line 244, in __init__
self.add_wb_master(bridge.wishbone)
File "[...]/litex/soc/integration/soc_core.py", line 202, in add_wb_master
self.bus.add_master(master=wbm)
File "[...]/litex/soc/integration/soc.py", line 347, in add_master
master = self.add_adapter(name, master, "m2s")
File "[...]/litex/soc/integration/soc.py", line 316, in add_adapter
bridge_cls = {
KeyError: (<class 'migen.genlib.record.Record'>, <class 'litex.soc.interconnect.wishbone.Interface'>)
2020-08-22 11:00:42 +02:00
Florent Kermarrec
792013a175
mac/sram: avoid asynchronous read port on LiteEthMACSRAMReader (fix the resource usage issue identified in #43 ).
2020-07-13 11:27:25 +02:00
Florent Kermarrec
1d76d02ea6
frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream).
2020-07-13 10:08:50 +02:00
enjoy-digital
dbe15f17fc
Merge pull request #42 from shuffle2/padding
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mac padding: fix counter reset value
2020-06-26 15:43:07 +02:00
Shawn Hoffman
d66d302567
mac padding: fix counter reset value
2020-06-25 03:26:37 -07:00
Florent Kermarrec
b1bcfb2073
mac/LiteEthMACCoreCrossbar: remove unnecessary fifos.
2020-06-22 14:54:26 +02:00
Florent Kermarrec
8e1185711b
common: remove Port.connect and use 2 separate Record.connect.
2020-06-22 14:36:44 +02:00
Florent Kermarrec
17caf17c9e
mac/LiteEthMACCoreCrossbar: remove cpu_dw.
2020-06-19 22:06:53 +02:00
Florent Kermarrec
23b420a2dd
mac/LiteEthMAC: simplify hybrid mode and avoid some duplication.
2020-06-19 22:01:22 +02:00
Florent Kermarrec
51cd54602b
core/mac: add missing separators, fix typos.
2020-06-19 19:59:53 +02:00
Florent Kermarrec
59d3336bec
mac: add separators, improve indent, minor simplifications.
2020-06-19 19:42:25 +02:00
Florent Kermarrec
d06c7b49a2
frontend: add separators, improve indent, minor simplifications.
2020-06-19 19:21:24 +02:00
Florent Kermarrec
2d58f489ea
core: improve indent.
2020-06-19 19:12:12 +02:00
Florent Kermarrec
c26281882a
core: add separators.
2020-06-19 19:02:28 +02:00