85 commits

Author	SHA1	Message	Date
Florent Kermarrec	4edba99b38	phy: remove s6rgmii (not working correctly). ... Alternative is to create a wrapper around the rgmii_if from Xilinx as it's done in opsis-soc	2018-07-18 10:09:01 +02:00
Florent Kermarrec	40d91f09c4	phy: use rx_dv instead of dv	2018-07-05 10:48:17 +02:00
Florent Kermarrec	a2dbdd6d2b	phy: add a7_1000basex phy (from misoc)	2018-06-29 14:26:19 +02:00
Florent Kermarrec	79a6ba7709	replace litex.gen imports with migen imports	2018-02-23 13:40:09 +01:00
Felix Held	20af2bf201	Fix all remaining indentation issues in python code ... I ran a script that shouldn't have missed any tab in the python source files.	2018-01-13 13:23:18 +11:00
Florent Kermarrec	b870d13d96	global: reset_less optimizations	2017-07-01 11:22:26 +02:00
Florent Kermarrec	a189b2c195	phy/s6rgmii: fix missing last signal	2016-03-29 16:53:37 +02:00
Florent Kermarrec	657ba4cb16	global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)	2016-03-16 21:36:07 +01:00
Florent Kermarrec	aff07c6809	global: use new StrideConverter	2016-03-16 17:01:13 +01:00
Florent Kermarrec	51f56e79dd	global: remove use of sop	2016-03-16 16:22:00 +01:00
Florent Kermarrec	32243934fb	global: use stream.Endpoint instead of Sink/Source (deprecated)	2016-03-15 16:50:00 +01:00
Florent Kermarrec	9593e29756	global: use 192.168.1.100 (remote)/ 192.168.1.50 (local) IP addresses	2016-03-15 15:40:06 +01:00
Florent Kermarrec	b7efe0fd46	phy: remove pads_register parameter (does not save enough, priority to simplicity)	2016-03-15 15:33:36 +01:00
Florent Kermarrec	5583fe5543	phy/s6rgmii: RenameClockDomains --> ClockDomainsRenamer	2016-02-24 23:51:31 +01:00
Florent Kermarrec	d38612db0c	remove use of Record.connect	2015-12-27 12:26:01 +01:00
Florent Kermarrec	1f19518d63	phy/common: add LiteEthPHYHWReset and use it on phys	2015-12-09 16:57:02 +01:00
Florent Kermarrec	54d7c6620b	phy: add mdio on all phys	2015-12-09 16:42:35 +01:00
Florent Kermarrec	ad0b4a165f	phy: rmii refactor (tested)	2015-12-07 15:46:15 +01:00
Florent Kermarrec	6006186fe0	phy/rmii: use 50MHz (instead of 100Mhz) and use DDROutput to generate ref_clk	2015-12-03 23:47:08 +01:00
Florent Kermarrec	09e6b3a8d7	phy: add s7rgmii	2015-12-01 01:34:06 +01:00
Florent Kermarrec	6b39b0f674	phy: fix clock domains renaming (ClockDomainsRenamer refactoring issue)	2015-11-30 13:04:47 +01:00
Florent Kermarrec	449d84bf11	remove Counter module	2015-11-24 21:02:07 +01:00
Florent Kermarrec	9a7039ef72	use mininal imports	2015-11-24 20:44:00 +01:00
Florent Kermarrec	09dad1b520	phy/rmii: adapt to new syntax and fixes	2015-11-19 15:42:51 +01:00
Florent Kermarrec	94e5c254eb	fix some imports	2015-11-14 20:17:47 +01:00
Florent Kermarrec	c1d7f2d427	phy: rename sim to model and remove from autodetect	2015-11-14 03:43:27 +01:00
Florent Kermarrec	7b9dc92b0b	for now use our fork of migen	2015-11-13 14:48:53 +01:00
Florent Kermarrec	a032168997	start adapting to new migen/litex	2015-11-12 19:52:59 +01:00
Florent Kermarrec	e2292d17f8	phy/gmii: enable use of gmii phy on non Xilinx devices	2015-10-25 10:57:44 +01:00
Florent Kermarrec	2b6dfa6a7e	cleanup (remove use of FlipFlop)	2015-10-24 13:28:09 +02:00
Florent Kermarrec	a6415c08b4	liteeth/phy/mii: use same code than liteeth_mini	2015-10-23 20:15:03 +02:00
Florent Kermarrec	7321e87cbb	phy: add RMII phy (not yet tested) assuming 100MHz cd_eth ClockDomain provided externally	2015-10-15 21:20:55 +02:00
Florent Kermarrec	e61c229bbb	simplify organization (try to regroup layers in single files)	2015-10-02 10:38:43 +02:00
Florent Kermarrec	306162096b	fix imports	2015-09-08 09:55:43 +02:00
Florent Kermarrec	20fc519410	init repo	2015-09-07 13:29:34 +02:00