9d22266233
frontend/stream: Update to LiteXModule and fix UDPTX packet send condition.
2023-06-14 11:17:37 +02:00
381ed30583
phy/k7_1000basex: Connect tx/rx_reset_done.
2023-06-13 19:18:29 +02:00
99d0fd92f3
phy/usp_gth_1000basex: Remove non-present/commented signals.
2023-06-13 19:13:40 +02:00
706f068822
phy/ku/usp_gth/gty_1000basex: Add rx/tx_polarity parameters for consistency with others 1000basex PHYs.
2023-06-13 19:12:04 +02:00
6c9dde1aca
phy/ku/usp_gth/gty_1000basex: Add with_csr parameter for consistency with other 1000basex PHYs.
2023-06-13 19:08:24 +02:00
3e026795d8
bench/xcu1525/xu8_st1: Directly add IOs in Etherbone section.
2023-06-13 18:36:15 +02:00
af5b9f433f
README: Add PHY support/family table.
2023-06-13 18:09:15 +02:00
9f69850697
usp_gth_1000basex: Working :), remove debug.
2023-06-13 17:44:12 +02:00
cfe3201854
phy/usp_gty_1000basex: Working :), remove debug.
2023-06-13 17:30:20 +02:00
bea94efae1
bench: Add Mercury XU8/ST1 bench to test/validate USP_GTH_1000BASEX.
2023-06-13 16:46:49 +02:00
d7aca70058
phy: Add initial usp_gth_1000basex (untested).
2023-06-13 16:41:26 +02:00
263eb1244f
phy: Rename usp_1000basex to usp_gty_1000basex and update xcu1525.
2023-06-13 16:33:22 +02:00
ee9d9e30e4
phy/1000basex: Move Gearbox to pcs_1000basex since common and rename it to PCSGearbox.
2023-06-13 16:27:14 +02:00
be9f26e876
phy/k7_1000basex: Improve TX/RX init and add TX/RX polarity support.
2023-06-13 15:23:38 +02:00
5400515a1e
phy/k7_1000basex: Replace specific TX/RX MMCM with S7MMCM.
2023-06-13 14:48:55 +02:00
9a67f4ea6b
phy/a7_1000basex: Cleanup BUFH presentation.
2023-06-13 14:48:02 +02:00
d63b340e34
bench: Add kc705 / K7_1000BASEX bench design.
2023-06-13 14:42:40 +02:00
fa08ce1ccc
bench: Update.
2023-06-13 14:13:03 +02:00
6d26f35ee4
phy/a7_1000basex: Make CSR optional (as done on k7_1000basex).
2023-06-13 13:56:18 +02:00
e8efca804b
phy/a7_1000basex: Replace specific TX/RX MMCM with S7MMCM.
2023-06-13 13:43:12 +02:00
5f2643ee83
phy/xgmii: Revert some changes since failing in CI.
2023-06-13 13:30:49 +02:00
5569cef1e2
phy/1000basex: Minor cleanups.
2023-06-13 10:42:40 +02:00
325f39b1cd
phy/pcs_1000basex: stb/ack -> valid/ready.
2023-06-13 10:16:43 +02:00
a9e41ef59b
phy/pcs_1000basex: Minor changes/cleanups.
...
- Switch to LiteXModule.
- Cosmetic cleanups for similarity with others modules.
- Use K/D definition from litex.soc.cores.code_8b10b.
2023-06-13 10:13:32 +02:00
7046987ff1
phy/pcs_1000basex: Update from misoc.
2023-06-13 09:52:20 +02:00
e9605ef9d8
phy/gmii/mii/rmii/xgmii: Switch to LiteXModule and minor simplifications/cleanups.
2023-06-13 09:35:17 +02:00
028838e744
phy/usp_1000basex: Update parameters from Xilinx PMA/PCS core.
2023-06-12 16:28:17 +02:00
150710d810
phy/usp_1000basex: Fix TX/RX_PROGDIV_CFG.
...
TX and RX clks now up.
2023-06-09 15:20:36 +02:00
8f7a1bf5d4
liteeth_gen: Disable wip Etherbone.
2023-06-09 08:32:42 +02:00
7f4df17615
liteeth_gen: Add initial (and wip) etherbone support.
2023-06-08 22:04:45 +02:00
f00d95c534
usp_1000basex: Update a few parameter and add debug probes to investigate on xcu1525.
2023-06-08 17:56:37 +02:00
a57178ac26
phy/rmii: Add with_refclk_ddr_ouptut parameter and minor cosmetic cleanups.
...
Setting with_refclk_ddr_ouptut to False can allow use of RMII PHY on platforms
not supporting DDROutput.
2023-05-24 19:18:53 +02:00
bbed8f1c95
Merge pull request #133 from jersey99/usp-rgmii
...
Make phy/usrgmii.py Ultrascale+ compatible
2023-05-18 08:38:29 +02:00
7040b19937
make phy/usrgmii.py Ultrascale+ compatible
2023-05-17 14:56:20 -07:00
d607d9f34b
setup.py: Prepare for 2023.04.
2023-05-07 20:48:15 +02:00
117fb37b24
Merge pull request #132 from timkpaine/tkp/ci
...
add manifest, uplift setup.py to pass twine checks
2023-04-15 22:17:39 +02:00
d66457d2b0
add manifest, uplift setup.py to pass twine checks
2023-04-11 14:18:11 -04:00
c30a6f8cd3
ecp5rgmii: Add way to set external TX clock to avoid loop clock
2023-03-13 11:00:46 +01:00
641c5dbdc7
Add core CDC depth and buffered parameters.
2023-02-16 22:49:11 +01:00
97dccdb294
Merge pull request #124 from sensille/wishbone_rx
...
wishbone rx data corruption
2022-12-20 09:53:34 +01:00
004e3f59d7
mac: fix typo
2022-12-08 18:11:01 +01:00
2b6d4ee51b
wishbone: fix race condition in rx path
...
When no rx slot is available, the current code path sends the FSM through
DISCARD-REMAINING to TERMINATE, which tries to signal the slot to the user
even though nothing has been received. This can lead to data corruption.
2022-12-08 17:58:25 +01:00
0e1a1da036
liteth_gen: eth_bus_standard -> bus_standard.
2022-11-21 12:13:57 +01:00
8052afea79
liteeth_gen: add_wb_master -> bus.add_master.
2022-11-21 12:04:52 +01:00
e3176c9386
phy/k7_1000basex: Make CSR optional and allow external reset control.
2022-11-04 12:11:51 +01:00
8680f74de0
Merge pull request #120 from suarezvictor/master
...
Add support for AXI-Lite bus in generator
2022-11-02 15:24:49 +01:00
68326dafd0
minimal core reorganization
2022-11-01 11:09:32 -03:00
5f14bd4a7f
add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file)
2022-10-31 20:43:53 -03:00
022207c5c6
liteeth_gen: Use fixed CSR mapping to avoid moving base addresses with LiteX changes/simplifications.
2022-10-24 09:10:24 +02:00
e9cdaa01a5
ci: Bump to ubuntu 20.04.
2022-10-14 18:17:35 +02:00
Florent Kermarrec
Vamsi Vytla
Tim Paine
rowanG077
Arne Jansen
Victor Suarez Rovere