1e35d78512
ocp_tap_timecard: Add initial SMAIOs peripherals to allow using SMA over PCIe DMA or also with direct (and slow) control/visualization with CSR registers.
2023-01-13 10:08:44 +01:00
fc7154a632
ocp_tap_timecard: Add Leds/I2C/PMOD/GPS/SMAs IOs.
2023-01-13 09:14:05 +01:00
a0fd3e7536
Add initial OCP-TAP TimeCard support with PCIe/SPIFlash/Leds/Buttons/DNA/XADC (Compiles but untested).
2023-01-12 18:50:23 +01:00
7a911b8ff6
Allow building digilent_arty using f4pga
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Only use XADC() and DNA() functions if vivado is the current toolchain.
2023-01-06 16:09:56 -06:00
764f64ff1e
nx_vip: Add missing 'origin' to SRAM SocRegions
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-04 12:02:11 +01:00
f5643e7c78
machdyne: Fix LiteDRAM PHYs imports (QuarterRateGENSDRPHY not already working?/integrated).
2023-01-01 21:35:51 +01:00
563ccbd8cf
Merge pull request #464 from machdyne/master
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initial support for machdyne konfekt and noir
2023-01-01 16:12:51 +01:00
5de6865cbe
Merge pull request #463 from stone3311/master
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terasic_deca: add SPI SD card support
2023-01-01 16:10:30 +01:00
fec82c59e2
remove konfekt ethernet option
2022-12-30 17:36:52 +01:00
f0dc9a6874
initial support for machdyne konfekt and noir
2022-12-30 17:00:35 +01:00
6cfb56bb07
terasic_deca: add SPI SD card support
2022-12-28 02:13:06 +01:00
57845d1ca4
Correct pinout and IOStandard
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Correct connector pinout
Correct pinout for ETH
LED IOStandard set to LVCMOS33
BTN[0] IOStandard set to LVCMOS33
Changes are made based on Tang_primer_20K_3690 and Tang_Primer_20K-Dock_3709 schemes.
2022-12-22 18:30:36 +03:00
4e06e5ff9c
targets/xilinx_zybo_z7: adding missing variant parameter to the platform
2022-12-14 07:47:09 +01:00
a92fdffb35
platforms/digilent_zybo_z7: reorder _io_x & _connectors_x, init cleanup
2022-12-12 22:17:39 +01:00
d28894a4b3
Reintroduce original Zybo + HDMI addition ( #461 )
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* Reintroduce original Zybo support
* Reintroduce original zybo, add HDMI + fixes for Z7
2022-12-12 22:05:47 +01:00
12db52471d
targets/jungle_electronics_fireant: Update SPIFlash (Make it similar to other boards with BIOS in SPIFlash).
2022-12-08 08:37:13 +01:00
c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config
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Arty z7 tcl config
2022-12-08 08:31:22 +01:00
71f1e1976b
Merge pull request #459 from tcal-x/icebitsy-ledchaser
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Add LedChaser to iCEBreaker-bitsy.
2022-12-06 09:05:37 +01:00
25c40ddda7
add gpio to board
2022-12-05 21:38:56 -03:00
6e205be83b
Add LedChaser to iCEBreaker-bitsy.
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Signed-off-by: Tim Callahan <tcal@google.com>
2022-12-04 17:58:20 -08:00
a889321535
targets/digilent_arty_z7: adding note to load gateware and bios
2022-12-03 16:54:52 +01:00
e71e3ab3ec
platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration
2022-12-03 16:54:39 +01:00
d0d90e9eef
Merge branch 'litex-hub:master' into master
2022-11-29 15:25:41 -03:00
b030630237
Merge pull request #453 from cklarhorst/zybo
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Zybo: Fix for Zynq7000 and use ps7 as submodule for Soft-CPUs
2022-11-25 21:48:43 +01:00
53b6bf035a
fixed parser
2022-11-24 16:03:12 +01:00
926ed21f0b
fixed review remarks; added zynq7000 as a submodule for using the ps as a slave
2022-11-23 17:20:25 +01:00
570ea11744
fix(plataform.basys_3): V_sync is pin R19
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Based in https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdc#LL129C34-L129C37
2022-11-23 09:16:50 -03:00
c489347a51
fixed zynq7000 integration; introduced option to add the processing-system as slave to the SoC
2022-11-18 11:19:57 +01:00
6f7716adbb
added config for ps7; introduced different variants for the zybo-board; fixed pins
2022-11-18 11:15:54 +01:00
892bf3546d
isx_im1283: connect CRG reset to PLL
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This fixes soft reset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-16 15:12:18 +08:00
e27d8c958e
isx_im1283: add jtagbone support
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Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-15 21:07:10 +08:00
ae47172d2a
targets/decklink_mini_4k: Update clock constraints.
2022-11-14 10:21:42 +01:00
6e10df234f
platforms/decklink_mini_4k: Fix data2_n pin (Thanks @rdolbeau).
2022-11-14 10:21:37 +01:00
e9d7013d70
sitlinv_stlv7325: add jtagbone support
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Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:28:04 +08:00
c2c59f5e8c
sitlinv_stlv7325: allow to set local/remote ip
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Port the script snippet from Colorlight i5 for setting the local/remote
IP address to STLV7325.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:58 +08:00
3d8106f84d
stlv7325: fix Ethernet IO voltages
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The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V.
Fix this in the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
27c3afb8fb
sitlinv_stlv7325: allow dynamic Ethernet IP
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Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.
Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
4ba5793822
sitlinv_stlv7325: remove unexistent COL/CRS pins
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The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.
Remove these pins from the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
1c07fa94ca
sitlinv_stlv7325: fix ident string vendor name
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As we changed the vendor name to proper Sitlinv in the file name, the
ident string is left untouched.
Fix this too.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
a8c92cd86f
targets/simple: Switch back to old version for now.
2022-11-08 11:55:06 +01:00
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
16b9677acd
targets: Switch to soc_core_argdict.
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The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
f1e24046fd
xilinx_alveo_u250: Fix.
2022-11-06 22:17:28 +01:00
6edfb2ca7a
Merge pull request #448 from trabucayre/fix_alinx_axu2cga_platform
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platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 22:11:25 +01:00
9a2028a9ba
targets: Remove useless argparse imports.
2022-11-06 22:09:21 +01:00
30723b1bb0
targets: Update targets that were still using argparse.ArgumentParser.
2022-11-06 22:07:17 +01:00
24cd983b8c
platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 21:52:00 +01:00
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
Florent Kermarrec
Luc Lagarde
gatecat
inc
stone3311
jiv4ik
Gwenhael Goavec-Merou
JoyBed
Guilherme Salustiano
Tim Callahan
Guilherme Salustiano
mkuhn99
Icenowy Zheng