27c242b2ca
targets/pcie: switch to PCIe X4 on all boards that support it.
2020-05-07 12:18:39 +02:00
f9939532b6
targets/pcie: update LitePCIe constraints.
2020-05-07 12:15:52 +02:00
d34c3baf15
prog: use different openocd config files for FT232/FT2232.
2020-05-06 16:14:51 +02:00
117d1a1c75
prog: add colorlight_5a_75b openocd config.
2020-05-06 16:01:59 +02:00
e500d90bcc
platforms/ecpix5: set pullups on rx_data to advertise as RGMII mode.
2020-05-06 16:00:46 +02:00
59e8c2cd30
acorn_cle_215: add .bin generation and --flash argument, working on hardware :).
2020-05-06 12:27:07 +02:00
a049fa6856
add Acorn CLE 215+ platform/target.
2020-05-06 07:53:55 +02:00
da61aabc5b
targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets.
2020-05-05 16:32:10 +02:00
b58b9b9e6a
platforms: fix CI.
2020-05-05 16:01:43 +02:00
2d9543b65e
targets: add build/load parameters on all targets.
2020-05-05 15:11:47 +02:00
19eb5708de
platforms: make sure all traditional platforms have a create_programmer method.
2020-05-05 13:34:57 +02:00
84468c2a63
targets/CRG: platforms are now automatically constraining the input clocks.
2020-05-05 11:51:57 +02:00
1f88a9d5ec
platforms: make sure clocks inputs are constraints on all platforms.
...
Also use new loose lookup_request to simplify constraints.
2020-05-05 11:45:41 +02:00
86648ec7d8
platforms/vcu118: rename ddram_second_channel to ddram:1.
2020-05-05 09:54:11 +02:00
e1820c7831
platforms/ac701: indent HPC.
2020-05-05 09:49:59 +02:00
2129b67779
platforms: make sure all plarforms have separators.
2020-05-05 09:47:55 +02:00
ea0eda9f75
platforms: make sure all Xilinx/Altera platforms have a create_programmer method, use OpenOCD on Spartan6 and 7-Series.
2020-05-05 09:42:34 +02:00
588bbac719
add prog directory with some Xilinx OpenOCD configurations files.
2020-05-05 09:11:06 +02:00
78b5727774
targets: rename usb_cdc to usb_acm.
...
As discussed recently on Discord.
2020-04-30 21:48:10 +02:00
2213d73b89
targets/kcu105: use cmd_latency=1.
2020-04-25 12:13:49 +02:00
a8a42c55c9
targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed.
2020-04-25 11:08:05 +02:00
865b01ec75
ecpix5: add ethernet.
2020-04-22 20:21:59 +02:00
6fe4c4ea62
ecpix5: add DDR3 (working)
2020-04-22 17:03:22 +02:00
efb13bc118
add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working.
2020-04-22 16:31:07 +02:00
4154bdf034
targets/PCIe: add PCIe software reset.
2020-04-20 12:30:09 +02:00
4ad6042e07
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:36:18 +02:00
4185a019f5
targets: manual define of the SDRAM PHY is no longer needed.
2020-04-16 11:25:59 +02:00
cb95962850
targets/ulx3s and colorlight_5a_75b: cleanup USB ACM addition and only keep USB ACM changes.
...
- remove update in loading/flashing: we need to thinks how to integrate this.
- remove specific README: documentation is moved to the files, link to more complete project can
be added if maintained externally, as done for the iCEBreaker for example.
- revert default freq on ULX3S to 50MHz and instantiate a second PLL as done on the colorlight.
2020-04-14 16:14:18 +02:00
f79a010a29
Addition of flash for colorlight board
2020-04-14 14:37:56 +01:00
389e8aa13a
Addition of USB ACM for ECP5
2020-04-14 13:53:46 +01:00
a12faae0fb
targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest).
2020-04-14 11:24:16 +02:00
52c9648176
arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
2020-04-13 15:20:36 +02:00
bbb1ded9f8
Added Arty S7 board
...
As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
2020-04-12 21:48:25 +02:00
188d4a45d6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:43:04 +02:00
ca197af2be
targets/simple: use CRG from litex.build.
2020-04-10 10:26:19 +02:00
b8a648d499
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:23:33 +02:00
4d7135f167
platforms/versa_ecp5: remove LatticeProgrammer (no longer used since we can now use OpenOCD).
2020-04-09 23:06:57 +02:00
2cf3c3e845
platforms: cosmetic cleanups.
2020-04-09 23:05:13 +02:00
df5de8816d
platforms/ulx3s: cleanup, fix user_leds, add PULLMODE/DRIVE constraints on SDRAM.
2020-04-09 18:53:06 +02:00
467b14a0ad
colorlight_5a_75b: minor comment changes.
2020-04-09 08:14:17 +02:00
15a27d40fa
targets/colorlight_5a_75b: Change baudrate to work on v6.1
...
There seems to be some capacitance on KEY+, so the usual 115200 don't work
2020-04-09 05:08:23 +02:00
4fc9df8414
colorlight_5a_75b/v6.1: Add eth_clock & serial pins
2020-04-09 05:06:08 +02:00
4ddde31429
colorlight_5a_75b/v6.1: Fix bank activate pin
2020-04-09 05:05:29 +02:00
9b3f16af1e
Merge pull request #62 from ilya-epifanov/ecp5-evn-button1-and-spi-flash-ios
...
ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-04-08 09:00:12 +02:00
db67dff0ea
targets/de10lite: use Max10PLL, remove 50MHz limitation.
2020-04-08 08:55:30 +02:00
8ccab03358
targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation.
2020-04-08 08:34:59 +02:00
4cdc121327
targets/de10nano: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:11:04 +02:00
2d8a4ef9ec
targets/de1_soc: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:07:37 +02:00
cec4cbb6dc
targets/de2_115: use CycloneIVPLL, remove 50MHz limitation.
2020-04-08 08:03:41 +02:00
1fac6077fb
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:01:58 +02:00
Florent Kermarrec
Dave Marples
Staf Verhaegen
David Sawatzke