Commit Graph

254 Commits

Author SHA1 Message Date
Florent Kermarrec 27f60b2e93 add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated).
Pinout from https://github.com/360nosc0pe project.
2020-11-13 12:20:15 +01:00
Florent Kermarrec d42af3ea19 targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
Florent Kermarrec 72afb95329 targets: create platform on BaseSoC for all targets (consitency). 2020-11-12 16:57:31 +01:00
Florent Kermarrec 843e724e3d targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe. 2020-11-12 16:39:42 +01:00
Florent Kermarrec 9f11bfb0d1 qmtech_ep4ce15: convert name to lowercase, minor cleanup and add to test_targets. 2020-11-12 14:33:45 +01:00
enjoy-digital 31eb74dc2d
Merge pull request #122 from baselsayeh/master
add Qmtech EP4CE15 coreboard support
2020-11-12 14:27:49 +01:00
Florent Kermarrec f3ccd140c2 targets/simple: add try/except on leds. 2020-11-12 14:26:00 +01:00
Basel Sayeh 0fc67ddfdb
update copyright 2020-11-12 15:25:39 +02:00
Florent Kermarrec 7c6df67739 targets: add tinyfpga_bx target (based on icebreaker/fomu targets). 2020-11-12 14:09:25 +01:00
Florent Kermarrec 302e4ffdff targets/simple: simplify (only keep minimal SoC + Leds) and add load argument.
ex of use:
./simple.py litex_boards.platform.ulx3s --build --load
./simple.py litex_boards.platform.trellisboard --build --load
./simple.py litex_boards.platform.arty --build --load
etc...
2020-11-12 13:54:30 +01:00
Florent Kermarrec 5cf7731f37 targets/netv2: add PCIe. 2020-11-12 12:16:01 +01:00
Florent Kermarrec 7a9f175450 targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block. 2020-11-12 12:08:20 +01:00
Florent Kermarrec 4401fec1e6 targets: remove add_csr("crg") (no longer needed). 2020-11-12 11:54:11 +01:00
Florent Kermarrec bd4e92ad13 targets: cleanup, uniformize build arguments between targets. 2020-11-12 11:46:00 +01:00
Basel Sayeh 1b1ed5ebf1
add Qmtech EP4CE15 coreboard support 2020-11-12 01:56:36 +02:00
Florent Kermarrec 5fbb176c2a targets/crosslink_nx: update NXLRAM import. 2020-11-09 11:05:18 +01:00
Florent Kermarrec afe44e2bd6 targets/crosslink_nx_evn: update NXPLL import. 2020-11-09 10:25:30 +01:00
Florent Kermarrec 39d979a9d3 targets/Ultrascale: add missing AsyncResetSynchronizer import. 2020-11-09 10:25:05 +01:00
davidcorrigan714 97b64d16a6 Lattice NX PLL Support 2020-11-08 20:34:46 -06:00
Florent Kermarrec 2b17dc1b89 target: add rst signal to CRG to allow full reset of the SoC on reboot command. 2020-11-04 11:13:42 +01:00
Florent Kermarrec aa6b9cab4a targets/crosslink_nx_vip: +x. 2020-11-04 09:30:57 +01:00
Florent Kermarrec ce14775dfb targets/tec0117: move SerialFlashManager import to flash function. 2020-11-04 09:30:31 +01:00
Florent Kermarrec c093d0d0fc platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:48:57 +01:00
Florent Kermarrec 8d26c241cd kc705: revert sys_clk_freq to 125MHz. 2020-11-02 19:51:48 +01:00
Florent Kermarrec babf638c2b targets/nexys_video: add SATA support. 2020-11-02 19:43:25 +01:00
Florent Kermarrec e950a4a588 targets/kc705: update sata pads. 2020-10-30 17:12:59 +01:00
Florent Kermarrec a410e447e1 targets/kc705/sata: enable write support. 2020-10-30 14:51:40 +01:00
Florent Kermarrec f9252fdd45 targets/kc705: simplify SATA using LiteX's add_sata integration method. 2020-10-29 10:16:40 +01:00
Florent Kermarrec 7da8628fba targets/kc705: switch SATA to gen2. 2020-10-28 19:09:30 +01:00
Florent Kermarrec 931f6667ac targets/kc705: add initial SATA support. 2020-10-26 15:15:24 +01:00
enjoy-digital 51934567fe
Merge pull request #118 from daveshah1/lifcl-vip
Add CrossLink-NX VIP board platform and target
2020-10-22 11:03:47 +02:00
Florent Kermarrec a38c1e7062 mist: add copyrights. 2020-10-22 10:48:58 +02:00
David Shah 20720693c4 crosslink_nx_vip: Add HyperRAM support
Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 09:15:40 +01:00
David Shah b278d8bccc Add CrossLink-NX VIP board platform and target 2020-10-22 09:15:35 +01:00
YanekJ 4541c39e94 Initial support for the MIST board (https://github.com/mist-devel/mist-board/wiki) 2020-10-17 12:28:22 +02:00
Florent Kermarrec 814e7630e4 targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it. 2020-10-13 12:10:29 +02:00
Florent Kermarrec 06137452d2 targets/xcu1525: use ddram_channel to select clk300. 2020-10-13 11:57:00 +02:00
Florent Kermarrec c3ea04b6e9 targets/s7/us: update sdram (manual cmd_latency no longer needed). 2020-10-12 18:46:21 +02:00
Florent Kermarrec ddf7038c78 ulx3s: add 1.7 and 2.0 revisions support. 2020-10-12 13:23:26 +02:00
Konrad Beckmann 5e67853a21 versa_ecp5: Add --eth-phy to select ethernet phy
This also simplifies the logic a bit.
2020-10-09 23:56:16 +02:00
Konrad Beckmann 477734ff06 versa_ecp5: Add etherbone support
Etherbone can be enabled with --with-etherbone
2020-10-09 00:53:08 +02:00
Florent Kermarrec fff20f7532 targets/fomu: base it on iCEBreaker target + USB-ACM.
This uniformizes Fomu target with others, provide a simple example of LiteX SoC
on Fomu and will ease maintenance.
2020-10-06 11:39:30 +02:00
enjoy-digital 79ef091a06
Merge pull request #110 from pepijndevos/gowin
Add initial support for Trenz TEC0117 board
2020-10-05 19:50:09 +02:00
enjoy-digital 062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc
crosslink_nx_evn: Improve documentation on UART jumpers
2020-10-02 09:40:04 +02:00
Pepijn de Vos 18e5def9f2 don't verify erase, very slow 2020-10-01 08:41:16 +02:00
Pepijn de Vos 81e4f1f158 add initial support for Trenz TEC0117 board 2020-09-30 14:01:36 +02:00
Florent Kermarrec de09b10726 targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment. 2020-09-24 18:19:49 +02:00
Florent Kermarrec cc53206aff targets/kcu105: create specific cd_eth for ethphy. 2020-09-24 10:25:55 +02:00
Florent Kermarrec 5b7288cfee targets/kcu105: add Etherbone support. 2020-09-24 09:55:11 +02:00
Florent Kermarrec 77ba49f2bb targets/pcie: update timing_constraints (now provided by the .xci). 2020-09-24 09:50:55 +02:00