4604379f46
platforms/sqrl_xcu1525: Revert previous commit, clk constraints were already present in DDR4 constraints.
2024-09-13 09:45:24 +02:00
90ff3d1ea9
platforms/sqrl_xcu1525.py: Add constraints on 300MHz clks.
2024-09-13 09:42:59 +02:00
1dbecf704d
efinix_ti375: Cosmetic cleanups on #610 .
2024-09-11 09:10:48 +02:00
d312ea331f
Merge pull request #610 from Dolu1990/ti375_c529
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Add efinix Ti375 c529 dev kit support
2024-09-11 08:18:44 +02:00
d0c07933bf
litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py: removed create_clkout name param, updated ClkOutput special
2024-09-10 16:37:12 +02:00
59d32e4283
targets/efinix_trion_t120_bga576_dev_kit.py: fix clock name to match sys_clk real name
2024-09-10 08:06:43 +02:00
d209f64a45
Add efinix_ti375_c529_dev_kit support
2024-09-05 15:30:55 +02:00
b893374cdf
Fix ti60 dev kit spi-sdcard voltage
2024-09-05 15:28:07 +02:00
c8603bebe4
targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv).
2024-09-04 22:06:40 +02:00
185f8d5da4
Merge pull request #603 from pepijndevos/apicula
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make Gowin boards work with Apicula
2024-09-04 10:40:10 +02:00
8f59ebeffb
WIP: make boards Gowin boards work with Apicula
2024-09-04 08:33:06 +02:00
738a5a8931
targets/efinix_trion_t120_bga576_dev_kit.py: added argument to select between RMII PMOD (default) or onboard RGMII Phy
2024-09-03 19:16:39 +02:00
7f26f3940f
efinix_trion_t120_bga576_dev_kit.py: fixed/rewire rx_ctl/tx_ctl (not compatible with DDIO mode), added message at build time
2024-09-03 16:01:51 +02:00
0313424fa0
targets/efinix_trion_t120_bga576_dev_kit.py: added argument to configure remote-ip. Pass local_ip and remote_ip to add_etherxxx
2024-09-03 12:42:49 +02:00
5a1e4bedfd
targets/efinix_titanium_ti60_f225_dev_kit.py: disable software_debug by default
2024-09-03 12:41:05 +02:00
0787517338
targets/efinix_titanium_ti60_f225_dev_kit.py: added argument to configure remote-ip. Pass local_ip and remote_ip to add_etherxxx
2024-09-03 12:40:35 +02:00
21e42e5bf6
wip
2024-08-30 20:35:38 +02:00
e7d00a8c43
ti60_f225_dev_kit: Update to new HyperRAM core with 2:1 ratio.
...
Tested at up to 250MHz sys_clk -> 125MHz HyperRAM Clk.
2024-08-29 12:35:39 +02:00
fd4f9ac186
targets: Use KILOBYTE/MEGABYTE constants when possible.
2024-08-29 12:18:19 +02:00
664525471f
Got HDMI to work on hardware
2024-08-28 20:19:33 +02:00
5bfde29ce4
platforms/lattice_certuspro_nx_evn.py: fix led pinout
2024-08-28 17:02:05 +02:00
c5d1a252c5
targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM.
2024-08-28 15:53:53 +02:00
30e26cacac
Add sdcard and usb ohci support
2024-08-27 08:31:53 +02:00
abaa9c404c
Fix the reset
2024-08-26 18:27:55 +02:00
144462e862
add jtag
2024-08-26 18:08:09 +02:00
d2cc8ad815
Got LPDDR4 to work
2024-08-26 16:54:53 +02:00
e604745c7d
wip
2024-08-26 13:05:57 +02:00
0f8b8defb4
efinix ti375 c529 dev kit bios OK
2024-08-26 11:29:27 +02:00
4002b8167c
Merge pull request #602 from trabucayre/fix_tangPrimer20k_iostandard
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platforms/sipeed_tang_primer_20k.py: fix IOStandard values
2024-08-19 17:14:25 +02:00
52fc033bf5
Merge pull request #599 from trabucayre/sipeed_tang_gw5A_SDRAM
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Sipeed tang gw5 a sdram
2024-08-19 17:12:48 +02:00
a5ee3c807a
platforms/sipeed_tang_primer_20k.py: fix IOStandard values
2024-08-14 09:16:39 +02:00
b1a6da84b3
sipeed_tang_primer_25k: add SDRAM support (j3 connector), allows user to select between mister and sipeed SDRAM module
2024-08-04 12:14:56 +02:00
2fa838b79d
sipeed_tang_mega_138k_pro: added SDRAM sipeed variant, allows user to select between mister and sipeed SDRAM module, fix sipeed SDRAM memory module
2024-08-04 12:13:47 +02:00
241dfb6780
fix pinnumber on connector C
2024-08-01 19:14:49 +02:00
81209b9fd1
platforms/enclustra_mercury_xu8_pe3: Revert to VivadoProgrammer since OpenFPGALoader is not albe to load bitstream correctly if FPGA is not already configured.
2024-07-22 15:28:25 +02:00
938bf8b3a6
targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR
2024-07-22 15:18:27 +02:00
ab732011b3
plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required to have access to the flash), added default clk period constraints
2024-07-22 14:49:03 +02:00
5d4ebeb09c
targets: Add initial Enclustra Mercury+ XU8/PE3 target with DRAM and PCIe.
2024-07-22 11:40:19 +02:00
0394b626fa
platforms/enclustrat_mercury_xu8_pe3: Switch to OpenFPGALoader for loading FPGA.
2024-07-22 11:39:17 +02:00
8f8e0bd228
targets/enclustra: Add Enclustra to identifier.
2024-07-22 11:38:22 +02:00
f844d06da2
targets/litex_acorn_baseboard_mini: Add detect_ftdi_chip method since newer batch of baseboard is mounted with FTDI ft4232 chips.
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FT2232 and FT4232 chips are footprint compatible but still need to be handled differently from software.
2024-07-19 15:43:25 +02:00
6d3c87a6f7
platforms/lattice_certuspro_nx_versa: Fix default_clk.
2024-07-17 15:14:53 +02:00
fff2e6bd3f
platform: Add Lattice CertusPro-NX Versa initial support.
2024-07-17 14:53:12 +02:00
88ab3eca6f
targets: Map SPRAM to SRAM when use as SRAM.
2024-07-17 11:01:34 +02:00
524387b45d
sqrl_xcu1525: Fix typo.
2024-07-11 12:54:38 +02:00
e94e84eb16
sqrl_xcu1525: Add more QSFP IOs.
2024-07-10 18:20:01 +02:00
c7b436a202
sqrl_xcu1525: Add QSFP-0/1 ref clks and rearrange a bit naming.
2024-07-10 17:04:48 +02:00
00df115e86
sqrl_xcu1525: Add QSFP-0/1 IOs.
2024-07-10 16:44:12 +02:00
5870b078f8
platforms/xilinx_vcu118: add fmc and pmod connector pinouts
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VCU118 board has one FMC HPC, one FMC+ HSPC and two PMOD connectors,
Vivado board files does not contain pinouts for these, so pinouts are
taken from VCU118 Evaluation Board User Guide (UG1224).
Signed-off-by: Yichuan Gao <gaoyichuan000@gmail.com>
2024-07-06 00:16:53 +08:00
15c6f89b1a
#570 : Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007 .
2024-07-05 10:26:28 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
Dolu1990
Pepijn de Vos
Gwenhael Goavec-Merou
Malte
Yichuan Gao