2b1b9684de
targets/icebreaker: simplify CRG, just use a 12MHz sys_clk and por_clk for reset.
2020-03-07 18:25:26 +01:00
9416ddd84a
targets/icebreaker: simplify arguments and make it closer to others targets.
2020-03-07 18:13:02 +01:00
992f7066fa
targets/icebreaker: simplify leds.
2020-03-07 18:12:59 +01:00
682316214c
targets/icebreaker: use specific method to set Yosys/Nextpnr settings. Rename argument to nextpnr-xxyy.
2020-03-07 18:12:52 +01:00
f777d4b08c
targets/icebreaker: +x
2020-03-05 23:11:35 +01:00
6f517ad1d6
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 10:57:59 +01:00
d002059e0b
add Enclustra Mercury XU5 board
2020-03-05 10:52:32 +01:00
7776764580
Merge pull request #51 from esden/icebreaker
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Add iCEBreaker FPGA support
2020-03-05 10:35:50 +01:00
745c99ba14
icebreaker: Updated to build on newer litex. Disabled bios building.
2020-03-05 00:12:18 -08:00
3ac9d927a9
targets: icebreaker: Minor style fixes.
2020-03-05 00:12:18 -08:00
738967176c
targets: icebreaker: set the boot address to point to SPI flash
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
093e4913c4
targets: icebreaker: hack to get boot working
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
77b780eb4b
targets: icebreaker: switch to single SPI
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The Icebreaker doesn't have the QE/ bit set in config, so default to
using single SPI.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
e6dcdc31ed
targets: icebreaker: fix cpu and add spi flash
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
0185095782
targets: icebreaker: fix argument parsing for cpu
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
f0dd31f6c8
target: targets: add crg and begin getting it working
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
ce9b67e2ee
Added icebreaker platform and target.
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Target is heavily based on Fomu.
2020-03-05 00:12:18 -08:00
fd6c555117
Merge pull request #50 from TomKeddie/tomk_20200228_colorlight_connectors
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platforms/colorlight_5a_75b: add J1-J8 connectors
2020-02-28 19:11:30 +01:00
7b4ca20ff4
platforms.colorlight_5a_75b: add J1-J8 connectors
2020-02-28 06:09:44 -08:00
be5ed35871
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:46:54 +01:00
b44885d222
vc707: fix copyrights (Michael Betz is the initial author)
2020-02-28 08:39:52 +01:00
b89af28a05
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
2020-02-27 12:58:52 +01:00
edcc2cf63e
test_targets: add vc707, zcu104, vcu118 and colorlight_5a_75b
2020-02-27 11:17:28 +01:00
aaa10c69eb
platforms/colorlight_5a_75b: add default_clk_name/period
2020-02-27 11:16:49 +01:00
d8de4fbdfb
platforms/targets: keep in sync with LiteX
2020-02-27 11:06:53 +01:00
18f65a7f9d
platforms/kc705: cleanup ddram.
2020-02-27 11:06:35 +01:00
d4460c11a5
platforms/kcu105/vcu118: remove PRE_EMPHASIS/EQUALIZATION on dm.
2020-02-27 10:43:41 +01:00
58f588f69e
platforms/zcu104/ddram: add PRE_EMPHASIS/EQUALIZATION settings
2020-02-27 10:43:01 +01:00
d87b8b3c66
zcu104: add separate ddram_32/64 definitions and use ddram_32 for now.
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Ease switching between ddram_32 and ddram_64.
2020-02-27 10:05:17 +01:00
8ecfb13f3c
zcu104: add copyrights
2020-02-27 09:57:26 +01:00
22b0449509
Merge pull request #47 from antmicro/zcu104
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Add support for ZCU104 board
2020-02-27 09:51:54 +01:00
608541d5b8
add ZCU104 board
2020-02-26 13:53:21 +01:00
e516ff3452
vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:16:51 +01:00
9d2ca50c5f
kcu105/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:16:35 +01:00
83d2c71099
platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks
2020-02-25 18:32:42 +01:00
4a84e9b08a
targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool
2020-02-25 12:47:08 +01:00
f279fe9d33
vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
2020-02-25 10:35:18 +01:00
3581df5af6
vc707: cleanup platform/targets, remove Ethernet support (SGMII is not currently supported)
2020-02-25 09:41:53 +01:00
88a1f80db1
vc707/vcu118: use proper copyrights
2020-02-25 09:03:52 +01:00
e34654fc8c
Merge pull request #46 from fei-g/master
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add new board files for VC707 and VCU118
2020-02-25 08:46:52 +01:00
373e74f435
add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
2020-02-24 14:20:47 -05:00
133f735e1f
Merge pull request #45 from trabucayre/fix_colorlight5A-75B_SDRAM
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platforms/colorlight_5a_75b.py: fix sdram_clock and sdram a pins
2020-02-24 08:30:18 +01:00
2cf4e084ec
platforms/colorlight_5a_75b.py: fix sdram_clock and sdram a pins
2020-02-23 10:01:41 +01:00
f72e7bd314
Merge pull request #41 from lromor/fix-wrong-import
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Changed wrong imports for fomu board.
2020-02-12 18:48:13 +07:00
ec30cc05c3
Changed wrong imports for fomu board.
2020-02-12 12:40:07 +01:00
c94360c2e0
targets: avoid direct use of mem_decoder.
2020-02-11 21:59:42 +01:00
4edf196911
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:45:35 +01:00
83c48946ad
test/test_targets: make sure all platforms are tested.
2020-02-03 10:04:14 +01:00
c3d8c7462d
test/test_targets: update
2020-02-03 09:44:22 +01:00
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
2020-02-03 09:36:30 +01:00
Florent Kermarrec
Jędrzej Boczar
Piotr Esden-Tempski
Sean Cross
Tom Keddie
Piotr Binkowski
Fei Gao
Gwenhael Goavec-Merou
Leonardo Romor