Commit Graph

321 Commits

Author SHA1 Message Date
Florent Kermarrec 588bbac719 add prog directory with some Xilinx OpenOCD configurations files. 2020-05-05 09:11:06 +02:00
Florent Kermarrec 78b5727774 targets: rename usb_cdc to usb_acm.
As discussed recently on Discord.
2020-04-30 21:48:10 +02:00
Florent Kermarrec 2213d73b89 targets/kcu105: use cmd_latency=1. 2020-04-25 12:13:49 +02:00
Florent Kermarrec a8a42c55c9 targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed. 2020-04-25 11:08:05 +02:00
Florent Kermarrec 865b01ec75 ecpix5: add ethernet. 2020-04-22 20:21:59 +02:00
Florent Kermarrec 6fe4c4ea62 ecpix5: add DDR3 (working) 2020-04-22 17:03:22 +02:00
Florent Kermarrec efb13bc118 add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working. 2020-04-22 16:31:07 +02:00
Florent Kermarrec 4154bdf034 targets/PCIe: add PCIe software reset. 2020-04-20 12:30:09 +02:00
Florent Kermarrec 4ad6042e07 platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables. 2020-04-18 11:36:18 +02:00
Florent Kermarrec 4185a019f5 targets: manual define of the SDRAM PHY is no longer needed. 2020-04-16 11:25:59 +02:00
Florent Kermarrec cb95962850 targets/ulx3s and colorlight_5a_75b: cleanup USB ACM addition and only keep USB ACM changes.
- remove update in loading/flashing: we need to thinks how to integrate this.
- remove specific README: documentation is moved to the files, link to more complete project can
be added if maintained externally, as done for the iCEBreaker for example.
- revert default freq on ULX3S to 50MHz and instantiate a second PLL as done on the colorlight.
2020-04-14 16:14:18 +02:00
enjoy-digital 4b4f2f9eb8
Merge pull request #67 from mubes/ecp5_usb
Addition of USB ACM for ECP5
2020-04-14 15:56:22 +02:00
Dave Marples f79a010a29 Addition of flash for colorlight board 2020-04-14 14:37:56 +01:00
Dave Marples 389e8aa13a Addition of USB ACM for ECP5 2020-04-14 13:53:46 +01:00
Florent Kermarrec a12faae0fb targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest). 2020-04-14 11:24:16 +02:00
Florent Kermarrec 52c9648176 arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets. 2020-04-13 15:20:36 +02:00
enjoy-digital 0cee59c48f
Merge pull request #65 from Fatsie/artys7
Added Arty S7 board
2020-04-13 15:06:29 +02:00
Staf Verhaegen bbb1ded9f8 Added Arty S7 board
As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
2020-04-12 21:48:25 +02:00
Florent Kermarrec 188d4a45d6 targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets. 2020-04-10 14:43:04 +02:00
Florent Kermarrec ca197af2be targets/simple: use CRG from litex.build. 2020-04-10 10:26:19 +02:00
Florent Kermarrec b8a648d499 litex.build: update from migen.genlib.io litex.build.io. 2020-04-10 09:23:33 +02:00
Florent Kermarrec 4d7135f167 platforms/versa_ecp5: remove LatticeProgrammer (no longer used since we can now use OpenOCD). 2020-04-09 23:06:57 +02:00
Florent Kermarrec 2cf3c3e845 platforms: cosmetic cleanups. 2020-04-09 23:05:13 +02:00
Florent Kermarrec df5de8816d platforms/ulx3s: cleanup, fix user_leds, add PULLMODE/DRIVE constraints on SDRAM. 2020-04-09 18:53:06 +02:00
Florent Kermarrec 467b14a0ad colorlight_5a_75b: minor comment changes. 2020-04-09 08:14:17 +02:00
enjoy-digital 7157b40718
Merge pull request #64 from david-sawatzke/improve_colorlight_v6.1
Improve compatability with colorlight 5a-75b v6.1
2020-04-09 08:05:23 +02:00
David Sawatzke 15a27d40fa targets/colorlight_5a_75b: Change baudrate to work on v6.1
There seems to be some capacitance on KEY+, so the usual 115200 don't work
2020-04-09 05:08:23 +02:00
David Sawatzke 4fc9df8414 colorlight_5a_75b/v6.1: Add eth_clock & serial pins 2020-04-09 05:06:08 +02:00
David Sawatzke 4ddde31429 colorlight_5a_75b/v6.1: Fix bank activate pin 2020-04-09 05:05:29 +02:00
Florent Kermarrec a80737e8b4 test/test_targets: fix typo. 2020-04-08 09:59:58 +02:00
enjoy-digital 9b3f16af1e
Merge pull request #62 from ilya-epifanov/ecp5-evn-button1-and-spi-flash-ios
ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-04-08 09:00:12 +02:00
Florent Kermarrec db67dff0ea targets/de10lite: use Max10PLL, remove 50MHz limitation. 2020-04-08 08:55:30 +02:00
Florent Kermarrec 9fe982150c test/test_targets: add c10lprefkit. 2020-04-08 08:35:33 +02:00
Florent Kermarrec 8ccab03358 targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation. 2020-04-08 08:34:59 +02:00
Florent Kermarrec 4cdc121327 targets/de10nano: use CycloneVPLL, remove 50MHz limitation. 2020-04-08 08:11:04 +02:00
Florent Kermarrec 2d8a4ef9ec targets/de1_soc: use CycloneVPLL, remove 50MHz limitation. 2020-04-08 08:07:37 +02:00
Florent Kermarrec cec4cbb6dc targets/de2_115: use CycloneIVPLL, remove 50MHz limitation. 2020-04-08 08:03:41 +02:00
Florent Kermarrec 1fac6077fb targets/de0nano: use CycloneIVPLL, remove 50MHz limitation. 2020-04-07 17:01:58 +02:00
Florent Kermarrec 5f629c203b targets/vcu118: fix clk500 typo. 2020-04-07 13:53:22 +02:00
Florent Kermarrec d7b9212044 .travis.yml: fix git clone error. 2020-04-07 12:22:02 +02:00
Florent Kermarrec 5e1da47cc4 setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
2020-04-07 12:01:45 +02:00
Florent Kermarrec a7fbe0a724 colorlight_5a_75b: add SoC with regular UART (on J19). 2020-04-03 10:28:53 +02:00
Florent Kermarrec 19e5366ad1 targets/colorlight_5a_75b: update sys/sys_ps phases. 2020-03-31 18:18:45 +02:00
Florent Kermarrec 9ae8a0cc11 colorlight_5a_75b/v7.0: add spiflash pins. 2020-03-31 16:18:12 +02:00
Ilya Epifanov a43072ac40 ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs 2020-03-28 13:08:46 +01:00
enjoy-digital ccfc021c1a
Merge pull request #61 from ilya-epifanov/ecp5-evn-programming
programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 12:59:19 +01:00
Ilya Epifanov 8afc9a5b03 programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy 2020-03-28 11:27:34 +01:00
Florent Kermarrec 89dd00d3a2 platforms/aller: rename pcie to pcie_x4 (for consistency with others platforms). 2020-03-27 13:01:36 +01:00
enjoy-digital cc2ac08ab9
Merge pull request #60 from antmicro/zcu104-sodimm
zcu104: add fully working SO-DIMM config
2020-03-26 18:30:27 +01:00
Piotr Binkowski d2edf54ab3 zcu104: add fully working SO-DIMM config 2020-03-26 16:37:11 +01:00