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42 Commits

Author SHA1 Message Date
Florent Kermarrec 5bd8c4d74f targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR banks (fixes Diamond build) 2019-11-01 10:52:56 +01:00
Florent Kermarrec 1ae26dd499 targets: use type="io" instead of io_region=True 2019-10-30 16:35:32 +01:00
Gabriel Somlo 8878c0a84a versa_ecp5, trellisboard: add trellis toolchain specific arguments 
Sync up with Litex commit #49372852d.
 2019-10-29 12:32:41 -04:00
Gabriel Somlo 5f80633154 targets: increase integrated ROM size if EthernetSoC used 
Sync up with litex commit #201218b2c.
 2019-10-29 12:32:41 -04:00
Florent Kermarrec 91083f99a8 ulx3s: simplify SDRAM module selection 2019-10-13 21:15:22 +02:00
enjoy-digital 6f3b194bd3
Merge pull request #20 from lolsborn/ulx3s-target 
memory device selection for ulx3s
 2019-10-13 20:59:16 +02:00
Steven Osborn abf6f7b09a memory device selection for ulx3s 2019-10-13 09:27:33 -07:00
enjoy-digital 53d5ed1226
Merge pull request #19 from lolsborn/ulx3s-target 
add sys clock freq flag, uses same method as current versa code
 2019-10-13 10:32:43 +02:00
Steven Osborn 34507eb431 add sys clock freq flag, uses same method as current versa code 2019-10-13 00:44:07 -07:00
Florent Kermarrec 785909ac5f targets: switch from shadow_base to io_regions 2019-10-09 11:09:59 +02:00
Sean Cross 19e2a12266
Merge pull request #18 from xobs/fomu-cpu-updates 
Fomu cpu updates
 2019-09-27 16:55:27 +08:00
Florent Kermarrec 48cd1208df targets: sync with litex targets 2019-09-25 14:09:25 +02:00
Florent Kermarrec 0ead12bae8 targets/ulx3s: revert to cl=2 2019-09-25 13:58:45 +02:00
Sean Cross c8e8f254ca targets: fomu: add USBSoC and default to heap placer 
The heap placer is important enough that we should just make it the
default.

Also, add a `USBSoC` that includes the required interrupt table, as this
must be specified prior to calling `__init__()`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-17 17:08:05 +08:00
Sean Cross 218bd353c1 targets: fomu: use memory array for sram address 
Use the memory array to find the address for the sram bank.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-17 17:07:26 +08:00
Sean Cross 348677598d targets: fomu: support building with a cpu 
Allow the user to specify a CPU.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-17 17:06:23 +08:00
Florent Kermarrec e94c6c8f27 partner/netv2: switch to MVP (K4B2G1646F instead of MT41J128M16) 2019-09-12 09:52:13 +02:00
Florent Kermarrec 91feb59f49 Merge branch 'master' of http://github.com/litex-hub/litex-boards 2019-09-11 23:02:44 +02:00
Florent Kermarrec a92ce32f91 targets/netv2: add clk100 (for framebuffer) 2019-09-11 23:02:21 +02:00
Antti Lukats 91a1520655 add initial Trenz Cyclone 10 LP RefKit support with SDRAM/HyperRAM/Ethernet 2019-09-10 11:32:29 +02:00
Florent Kermarrec c6bb34d78a partner/targets/nereid: MT8KTF51264 now in LiteDRAM 2019-09-09 08:50:06 +02:00
Florent Kermarrec b4eefa6c33 import: allow importing directly from litex_boards.platforms or litex_boards.targets 2019-09-03 15:30:20 +02:00
Florent Kermarrec ec5540454b partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic 2019-09-02 11:43:30 +02:00
enjoy-digital cd527f0fcb
Merge branch 'master' into master 2019-09-02 11:29:22 +02:00
Florent Kermarrec d78965ffb2 partner/targets/fomu fix copyright & mode 2019-09-02 11:23:43 +02:00
Sean Cross bdbd2ec1c0 partner: add fomu target 
This adds the Fomu target back in.  The default BaseSoC supports
various USB methods, and will be updated as more become available.

The debug bridge may optionally be added.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-02 14:18:09 +08:00
Florent Kermarrec e704014b36 targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them. 2019-09-01 11:43:21 +02:00
Rohit Singh 346621b9fc partner: add platforms and targets for aller, tagus and nereid boards 2019-09-01 03:02:04 -05:00
Florent Kermarrec f661ee0ec9 targets: fix import 2019-08-26 11:00:12 +02:00
Florent Kermarrec ac58d57a83 targets: import platforms from litex_boards.platforms 2019-08-26 09:09:40 +02:00
Florent Kermarrec b84308cb58 list all platforms/targets in platforms.py, targets.py to ease import 2019-08-26 09:07:07 +02:00
Florent Kermarrec 2596b20982 partner/targets/fomu: remove for now since only has a CRG (we'll add one later with a real design) 2019-08-07 09:08:11 +02:00
Florent Kermarrec bbf0e770e9 partner/targets/trellisboard: cleanup/update 2019-07-12 19:39:12 +02:00
Florent Kermarrec a792502756 targets: make sure all targets have copyrights & #!/usr/bin/env python3 2019-07-12 19:36:49 +02:00
Florent Kermarrec e470b55d2b fomu, trellisboard: +x 2019-07-12 19:24:08 +02:00
Florent Kermarrec a88970a67f move trellis board from community to partner 2019-07-12 19:23:21 +02:00
Florent Kermarrec 82d73b8359 Merge branch 'master' of http://github.com/litex-hub/litex-boards 2019-07-12 19:19:31 +02:00
Florent Kermarrec debafd7c17 official/partner: update 2019-07-12 19:19:01 +02:00
DurandA adcc34b528 Turn litex_boards.partner into module 2019-07-01 19:36:34 +02:00
Florent Kermarrec aeddb93729 add copyright header to all files, udpate. 2019-06-24 12:13:54 +02:00
Sean Cross d01711fdf9 partner: targets: add fomu target 
The `fomu` target represents a generic target that supports the Fomu
48 MHz crystal, with or without a PLL.

It does not yet include a BaseSoC, since that requires USB and
up5kspram, neither of which are present yet.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-19 12:58:13 -07:00
Florent Kermarrec 44d01edab9 dispatch platforms/targets by level of support 2019-06-10 18:59:49 +02:00