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739 Commits

Author SHA1 Message Date
Goran Mahovlic 99db2ae60d
Delete ulx4m_ld_v2.py 2023-02-13 11:48:51 +01:00
Goran Mahovlic 57c9cff39e
Update radiona_ulx4m_ld_v2.py 2023-02-13 11:45:48 +01:00
Goran Mahovlic 9320ae8b74
Fixing platform file 2023-02-13 11:44:59 +01:00
Goran Mahovlic a3815efccb
Adding radiona ULX4M-LD-V2 2023-02-11 16:57:34 +01:00
MV a354f04143 avoid undefined clocks by moving the derive*-statements to start of the additional constraints list 2023-02-09 15:58:41 +01:00
Florent Kermarrec b9874685a5 gadgetfactory_papilio_pro: Cosmetic cleanups. 2023-01-17 15:43:12 +01:00
enjoy-digital ec4d203eb6
Merge pull request #471 from Acathla-fr/papilio 
Target/Platform Papilio Pro added (with Arcade MegaWing)
 2023-01-17 11:21:27 +01:00
enjoy-digital 801008f5ad
Merge pull request #469 from hansfbaier/hpcstore-rename 
HPC FPGA Store on AliExpress renamed itself to SITLINV
 2023-01-17 11:20:19 +01:00
Fabien 05ef1ee09e Target/Platform Papilio Pro added (with Arcade MegaWing) 2023-01-16 13:41:24 +01:00
Florent Kermarrec 55fcb4cd47 xilinx_alveo_u2x0: Improve indentation on DRAMs. 2023-01-16 09:34:59 +01:00
Florent Kermarrec be77f82720 platforms/xilinx_alveo_u250: Fix dram numbering. 2023-01-16 09:31:23 +01:00
Florent Kermarrec e02f64a7db platforms/gsd_butterstick: Fix copyright. 2023-01-16 08:41:10 +01:00
Greg Davill 59a897e2dd
gsd_butterstick: Add missing pin defs 2023-01-16 17:32:39 +10:30
Hans Baier c0773ed9b9 HPC FPGA Store on AliExpress renamed itself to SITLINV 2023-01-16 11:31:35 +07:00
Florent Kermarrec 36a4100c8b ocp_timecard: Add DDR3 SDRAM support. 2023-01-13 12:41:34 +01:00
Florent Kermarrec 1e35d78512 ocp_tap_timecard: Add initial SMAIOs peripherals to allow using SMA over PCIe DMA or also with direct (and slow) control/visualization with CSR registers. 2023-01-13 10:08:44 +01:00
Florent Kermarrec fc7154a632 ocp_tap_timecard: Add Leds/I2C/PMOD/GPS/SMAs IOs. 2023-01-13 09:14:05 +01:00
Florent Kermarrec a0fd3e7536 Add initial OCP-TAP TimeCard support with PCIe/SPIFlash/Leds/Buttons/DNA/XADC (Compiles but untested). 2023-01-12 18:50:23 +01:00
enjoy-digital 563ccbd8cf
Merge pull request #464 from machdyne/master 
initial support for machdyne konfekt and noir
 2023-01-01 16:12:51 +01:00
enjoy-digital 5de6865cbe
Merge pull request #463 from stone3311/master 
terasic_deca: add SPI SD card support
 2023-01-01 16:10:30 +01:00
inc f0dc9a6874 initial support for machdyne konfekt and noir 2022-12-30 17:00:35 +01:00
stone3311 6cfb56bb07 terasic_deca: add SPI SD card support 2022-12-28 02:13:06 +01:00
jiv4ik 57845d1ca4
Correct pinout and IOStandard 
Correct connector pinout
Correct pinout for ETH
LED IOStandard set to LVCMOS33
BTN[0] IOStandard set to LVCMOS33
Changes are made based on Tang_primer_20K_3690 and Tang_Primer_20K-Dock_3709 schemes.
 2022-12-22 18:30:36 +03:00
Gwenhael Goavec-Merou a92fdffb35 platforms/digilent_zybo_z7: reorder _io_x & _connectors_x, init cleanup 2022-12-12 22:17:39 +01:00
JoyBed d28894a4b3
Reintroduce original Zybo + HDMI addition (#461) 
* Reintroduce original Zybo support

* Reintroduce original zybo, add HDMI + fixes for Z7
 2022-12-12 22:05:47 +01:00
enjoy-digital c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config 
Arty z7 tcl config
 2022-12-08 08:31:22 +01:00
Guilherme Salustiano 25c40ddda7 add gpio to board 2022-12-05 21:38:56 -03:00
Gwenhael Goavec-Merou e71e3ab3ec platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration 2022-12-03 16:54:39 +01:00
Guilherme Salustiano d0d90e9eef
Merge branch 'litex-hub:master' into master 2022-11-29 15:25:41 -03:00
mkuhn99 926ed21f0b fixed review remarks; added zynq7000 as a submodule for using the ps as a slave 2022-11-23 17:20:25 +01:00
Guilherme Salustiano 570ea11744
fix(plataform.basys_3): V_sync is pin R19 
Based in https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdc#LL129C34-L129C37
 2022-11-23 09:16:50 -03:00
mkuhn99 6f7716adbb added config for ps7; introduced different variants for the zybo-board; fixed pins 2022-11-18 11:15:54 +01:00
Florent Kermarrec 6e10df234f platforms/decklink_mini_4k: Fix data2_n pin (Thanks @rdolbeau). 2022-11-14 10:21:37 +01:00
Icenowy Zheng 3d8106f84d stlv7325: fix Ethernet IO voltages 
The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V.

Fix this in the platform definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Icenowy Zheng 4ba5793822 sitlinv_stlv7325: remove unexistent COL/CRS pins 
The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.

Remove these pins from the platform definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Gwenhael Goavec-Merou 24cd983b8c platforms/alinx_axu2cga: adding missing psu_config at platform level 2022-11-06 21:52:00 +01:00
Gwenhael Goavec-Merou 9960f38d95 targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser 2022-11-06 11:27:47 +01:00
Icenowy Zheng d7184fb043 stlv7325, a_e115fb: use the proper vendor name Sitlinv 
The boards are in fact from a vendor called 成都赛特凌威科技有限公司,
and their English registered trademark (used on the banner of their
Taobao store) is Sitlinv, which sounds like 赛特凌威.

Use this vendor name instead of where it's bought.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-10-30 10:51:13 +08:00
enjoy-digital 6c05ddae1b
Merge pull request #438 from shawnanastasio/nexys4_part_name 
platforms/nexys4*: Update part name
 2022-10-27 12:11:07 +02:00
Chema 125569b2cb add FPGAWars Alhambra II 2022-10-25 21:12:02 +02:00
enjoy-digital 474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283 
Add ISX iM1283 board
 2022-10-22 15:56:43 +02:00
Shawn Anastasio d4b2461b5a platforms/nexys4*: Update part name 
Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so
change it to xc7a100tcsg324-1 which works with both f4pga and Vivado.
 2022-10-21 14:15:27 -05:00
Florent Kermarrec 377cda05a3 ti60_f225_dev_kit: Switch 1.2V banks to 1.8V to fix compilation issues with latest Efinity. 
Will need to be investigated more.
 2022-10-20 18:21:52 +02:00
Icenowy Zheng 745ebbbfa1 Add ISX iM1283 board 
ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.

This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-10-14 22:50:43 +08:00
Florent Kermarrec 23c6acd013 platforms/ti60_f225_dev_kit: Fix IO voltage conflicts between peripherals/banks. 
Was already reported as a warning on 2021.1.165.2.19 but now an error with 2022.1.226.

Note: To get the build working with 2022.1.226 the following change had to be done to
pt/bin/writer/pinout.py, line 2254:
- table.add_rows(table_rows)
+ for table_row in table_rows:
+   table.add_row(table_row)
This would need to be investigated more to know if related to our local setup/machine.
 2022-10-14 10:22:54 +02:00
Florent Kermarrec 3b339ba9a3 platforms/xilinx_kc705: Fix flash proxy name. 2022-10-13 08:48:33 +02:00
Florent Kermarrec 99888c52ce xilinx_kc705/i2c: Add pullups. 2022-10-11 17:26:06 +02:00
Franck Jullien 3ec18c3583 Add qmtech Cyclone IV Starter Kit 2022-10-09 16:34:44 +02:00
Lukas F. Hartmann c38b8b1d8c MNT RKX7: update platform and target for D-2 release 2022-10-03 20:09:48 +02:00
Vadzim Dambrouski cf416d0d66 stlv7325: Adjust DDR3 pins to match reference design 2022-10-01 11:15:47 +02:00