f79a010a29
Addition of flash for colorlight board
2020-04-14 14:37:56 +01:00
389e8aa13a
Addition of USB ACM for ECP5
2020-04-14 13:53:46 +01:00
a12faae0fb
targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest).
2020-04-14 11:24:16 +02:00
52c9648176
arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
2020-04-13 15:20:36 +02:00
0cee59c48f
Merge pull request #65 from Fatsie/artys7
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Added Arty S7 board
2020-04-13 15:06:29 +02:00
bbb1ded9f8
Added Arty S7 board
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As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
2020-04-12 21:48:25 +02:00
188d4a45d6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:43:04 +02:00
ca197af2be
targets/simple: use CRG from litex.build.
2020-04-10 10:26:19 +02:00
b8a648d499
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:23:33 +02:00
4d7135f167
platforms/versa_ecp5: remove LatticeProgrammer (no longer used since we can now use OpenOCD).
2020-04-09 23:06:57 +02:00
2cf3c3e845
platforms: cosmetic cleanups.
2020-04-09 23:05:13 +02:00
df5de8816d
platforms/ulx3s: cleanup, fix user_leds, add PULLMODE/DRIVE constraints on SDRAM.
2020-04-09 18:53:06 +02:00
467b14a0ad
colorlight_5a_75b: minor comment changes.
2020-04-09 08:14:17 +02:00
7157b40718
Merge pull request #64 from david-sawatzke/improve_colorlight_v6.1
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Improve compatability with colorlight 5a-75b v6.1
2020-04-09 08:05:23 +02:00
15a27d40fa
targets/colorlight_5a_75b: Change baudrate to work on v6.1
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There seems to be some capacitance on KEY+, so the usual 115200 don't work
2020-04-09 05:08:23 +02:00
4fc9df8414
colorlight_5a_75b/v6.1: Add eth_clock & serial pins
2020-04-09 05:06:08 +02:00
4ddde31429
colorlight_5a_75b/v6.1: Fix bank activate pin
2020-04-09 05:05:29 +02:00
a80737e8b4
test/test_targets: fix typo.
2020-04-08 09:59:58 +02:00
9b3f16af1e
Merge pull request #62 from ilya-epifanov/ecp5-evn-button1-and-spi-flash-ios
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ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-04-08 09:00:12 +02:00
db67dff0ea
targets/de10lite: use Max10PLL, remove 50MHz limitation.
2020-04-08 08:55:30 +02:00
9fe982150c
test/test_targets: add c10lprefkit.
2020-04-08 08:35:33 +02:00
8ccab03358
targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation.
2020-04-08 08:34:59 +02:00
4cdc121327
targets/de10nano: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:11:04 +02:00
2d8a4ef9ec
targets/de1_soc: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:07:37 +02:00
cec4cbb6dc
targets/de2_115: use CycloneIVPLL, remove 50MHz limitation.
2020-04-08 08:03:41 +02:00
1fac6077fb
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:01:58 +02:00
5f629c203b
targets/vcu118: fix clk500 typo.
2020-04-07 13:53:22 +02:00
d7b9212044
.travis.yml: fix git clone error.
2020-04-07 12:22:02 +02:00
5e1da47cc4
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
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- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
2020-04-07 12:01:45 +02:00
a7fbe0a724
colorlight_5a_75b: add SoC with regular UART (on J19).
2020-04-03 10:28:53 +02:00
19e5366ad1
targets/colorlight_5a_75b: update sys/sys_ps phases.
2020-03-31 18:18:45 +02:00
9ae8a0cc11
colorlight_5a_75b/v7.0: add spiflash pins.
2020-03-31 16:18:12 +02:00
a43072ac40
ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-03-28 13:08:46 +01:00
ccfc021c1a
Merge pull request #61 from ilya-epifanov/ecp5-evn-programming
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programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 12:59:19 +01:00
8afc9a5b03
programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 11:27:34 +01:00
89dd00d3a2
platforms/aller: rename pcie to pcie_x4 (for consistency with others platforms).
2020-03-27 13:01:36 +01:00
cc2ac08ab9
Merge pull request #60 from antmicro/zcu104-sodimm
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zcu104: add fully working SO-DIMM config
2020-03-26 18:30:27 +01:00
d2edf54ab3
zcu104: add fully working SO-DIMM config
2020-03-26 16:37:11 +01:00
3b91e96c42
targets/add_constant: avoid specifying value when value is None (=default)
2020-03-26 09:47:22 +01:00
555bf6c4dc
targets/Ultrascale(+): enable USDDRPHY_DEBUG.
2020-03-26 09:17:09 +01:00
4053c02d7e
targets/orangecrab: add USB PLL for USB CDC with ValentyUSB.
2020-03-25 19:38:36 +01:00
85f38876c2
targets: update PCIe on Numato targets.
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Should be compatible with software from: https://github.com/enjoy-digital/netv2 .
2020-03-25 11:53:52 +01:00
6e6b6dac55
platforms/orangecrab: add spisdcard pins.
2020-03-25 10:21:57 +01:00
87fd4dc059
platforms/minispartan6: add spisdcard pins.
2020-03-25 09:53:04 +01:00
24033e331c
targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 19:59:42 +01:00
92f793f9c5
platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 19:58:12 +01:00
131733a2e6
Merge pull request #59 from gregdavill/OrangeCrab
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OrangeCrab Board updates
2020-03-23 07:17:56 +01:00
fe2fa097fa
test_targets: revert orangecrab test build
2020-03-23 09:20:41 +10:30
eb35ec92ba
orangecrab: combine revisions in target
2020-03-23 09:20:01 +10:30
357aeac59d
test_targets: Update orangecrab platforms
2020-03-22 21:25:39 +10:30
Dave Marples
Florent Kermarrec
Staf Verhaegen
David Sawatzke
Ilya Epifanov
Piotr Binkowski
Greg Davill