Florent Kermarrec
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2b43a18a3c
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platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv
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2019-12-31 18:18:56 +01:00 |
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Florent Kermarrec
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2259042383
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pipistrello: add copyrights
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2019-12-31 17:44:24 +01:00 |
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enjoy-digital
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6324433e1c
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Merge pull request #28 from zakgi/master
Adding initial support for Saanlima's Pipistrello LX45 board
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2019-12-31 17:33:25 +01:00 |
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Florent Kermarrec
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980b0ebda0
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targets/de10lite: rename VideoSoC to VGASoC (to avoid confusion with VideoSoC as used on Video designs with framebuffer)
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2019-12-31 17:30:23 +01:00 |
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Florent Kermarrec
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10e5248bda
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targets/de10lite: minor cleanup on import/_CRG
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2019-12-31 17:26:09 +01:00 |
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msloniewski
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9c5a4f757f
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targets/de10lite: add VideoSoC with VGA peripheral
Add VideoSoC build option, based on Frank Buss example.
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2019-12-30 23:25:43 +01:00 |
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msloniewski
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cace17e162
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targets/de10lite: refactor setting up clock domains
Use PLL to generate clock for both sys clock domain and clock domain
for sdram. Additionally set up clock domain for VGA periph.
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2019-12-30 23:25:43 +01:00 |
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Giammarco Zacheo
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39e428581f
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Adding initial support for Saanlima's Pipistrello LX45 board
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2019-12-29 18:29:11 -08:00 |
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Florent Kermarrec
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30ea463b41
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targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
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2019-12-06 16:01:59 +01:00 |
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Florent Kermarrec
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f7fbfb4639
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partner/community/targets: uniformize, improve presentation
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2019-12-03 09:33:08 +01:00 |
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Florent Kermarrec
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1ae26dd499
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targets: use type="io" instead of io_region=True
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2019-10-30 16:35:32 +01:00 |
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Florent Kermarrec
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785909ac5f
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targets: switch from shadow_base to io_regions
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2019-10-09 11:09:59 +02:00 |
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Florent Kermarrec
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b4eefa6c33
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import: allow importing directly from litex_boards.platforms or litex_boards.targets
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2019-09-03 15:30:20 +02:00 |
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Florent Kermarrec
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e704014b36
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targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
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2019-09-01 11:43:21 +02:00 |
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Florent Kermarrec
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f661ee0ec9
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targets: fix import
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2019-08-26 11:00:12 +02:00 |
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Florent Kermarrec
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ac58d57a83
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targets: import platforms from litex_boards.platforms
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2019-08-26 09:09:40 +02:00 |
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Florent Kermarrec
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b84308cb58
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list all platforms/targets in platforms.py, targets.py to ease import
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2019-08-26 09:07:07 +02:00 |
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Arnaud Durand
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618f41bb1e
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Update ecp5_evn.py
The system clock was driven directly while it should be driven by the PLL.
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2019-08-22 02:27:50 +02:00 |
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DurandA
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1abca7dcff
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Turn litex_boards.community into module
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2019-08-12 00:17:26 +02:00 |
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DurandA
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c90950e319
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Default to 60 Mhz system clock on ECP5 Evaluation Board
Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
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2019-08-09 11:58:30 +02:00 |
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DurandA
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4126ed21d5
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Add X5 clock and PLL to ECP5 Evaluation Board
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2019-08-09 11:54:38 +02:00 |
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DurandA
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c7444fe19c
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Add ECP5 Evaluation Board
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2019-08-09 09:45:13 +02:00 |
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Florent Kermarrec
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a88970a67f
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move trellis board from community to partner
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2019-07-12 19:23:21 +02:00 |
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David Shah
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a07e88d761
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community: Add TrellisBoard
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-09 15:52:28 +01:00 |
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Florent Kermarrec
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aeddb93729
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add copyright header to all files, udpate.
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2019-06-24 12:13:54 +02:00 |
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Florent Kermarrec
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44d01edab9
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dispatch platforms/targets by level of support
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2019-06-10 18:59:49 +02:00 |
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