Commit graph

46 commits

Author SHA1 Message Date
Sean Cross
bdbd2ec1c0 partner: add fomu target
This adds the Fomu target back in.  The default BaseSoC supports
various USB methods, and will be updated as more become available.

The debug bridge may optionally be added.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:18:09 +08:00
Florent Kermarrec
e704014b36 targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them. 2019-09-01 11:43:21 +02:00
Florent Kermarrec
1131af05af nexys_video: generate clk100 2019-08-27 14:05:07 +02:00
Florent Kermarrec
f661ee0ec9 targets: fix import 2019-08-26 11:00:12 +02:00
Florent Kermarrec
b21944c05a test/tests_targets: add kcu105/ecp5_evn and cleanup indent 2019-08-26 09:19:32 +02:00
Florent Kermarrec
ac58d57a83 targets: import platforms from litex_boards.platforms 2019-08-26 09:09:40 +02:00
Florent Kermarrec
b84308cb58 list all platforms/targets in platforms.py, targets.py to ease import 2019-08-26 09:07:07 +02:00
enjoy-digital
596a854061
Merge pull request #13 from DurandA/patch-1
Fix ecp5_evn clock
2019-08-26 06:52:48 +02:00
Arnaud Durand
618f41bb1e
Update ecp5_evn.py
The system clock was driven directly while it should be driven by the PLL.
2019-08-22 02:27:50 +02:00
enjoy-digital
e31360b1c6
Merge pull request #11 from DurandA/master
Turn litex_boards.community into module
2019-08-12 07:05:31 +02:00
DurandA
1abca7dcff Turn litex_boards.community into module 2019-08-12 00:17:26 +02:00
enjoy-digital
ad21f15782
Merge pull request #10 from DurandA/ecp5-evn
Add ECP5 Evaluation Board
2019-08-09 12:37:36 +02:00
DurandA
c90950e319 Default to 60 Mhz system clock on ECP5 Evaluation Board
Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
2019-08-09 11:58:30 +02:00
DurandA
9e6dccc277 Remove ECP5 Evaluation Board programmer 2019-08-09 11:54:49 +02:00
DurandA
4126ed21d5 Add X5 clock and PLL to ECP5 Evaluation Board 2019-08-09 11:54:38 +02:00
DurandA
c7444fe19c Add ECP5 Evaluation Board 2019-08-09 09:45:13 +02:00
Florent Kermarrec
2596b20982 partner/targets/fomu: remove for now since only has a CRG (we'll add one later with a real design) 2019-08-07 09:08:11 +02:00
Florent Kermarrec
0c1fa7f4a8 partner/platform/fomu: cleaup, make it similar to others platforms 2019-08-07 09:04:31 +02:00
Florent Kermarrec
9f3ed82097 keep up to date with LiteX
- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5
2019-08-07 08:47:08 +02:00
Florent Kermarrec
bbf0e770e9 partner/targets/trellisboard: cleanup/update 2019-07-12 19:39:12 +02:00
Florent Kermarrec
a792502756 targets: make sure all targets have copyrights & #!/usr/bin/env python3 2019-07-12 19:36:49 +02:00
Florent Kermarrec
83455ee08b test_targets: add trellisboard 2019-07-12 19:26:31 +02:00
Florent Kermarrec
e470b55d2b fomu, trellisboard: +x 2019-07-12 19:24:08 +02:00
Florent Kermarrec
a88970a67f move trellis board from community to partner 2019-07-12 19:23:21 +02:00
Florent Kermarrec
82d73b8359 Merge branch 'master' of http://github.com/litex-hub/litex-boards 2019-07-12 19:19:31 +02:00
Florent Kermarrec
debafd7c17 official/partner: update 2019-07-12 19:19:01 +02:00
enjoy-digital
1fdaf5dbf3
Merge pull request #7 from daveshah1/trellisboard
community: Add TrellisBoard
2019-07-09 17:06:22 +02:00
David Shah
a07e88d761 community: Add TrellisBoard
Signed-off-by: David Shah <dave@ds0.me>
2019-07-09 15:52:28 +01:00
enjoy-digital
7ba91154d7
Merge pull request #5 from DurandA/master
Turn litex_boards.partner into module
2019-07-08 15:01:28 +02:00
DurandA
adcc34b528 Turn litex_boards.partner into module 2019-07-01 19:36:34 +02:00
enjoy-digital
2817c943f5
Merge pull request #4 from DurandA/master
Add litex_boards package to setup.py
2019-07-01 18:56:36 +02:00
Arnaud Durand
baac94e0a4
Add litex_boards package to setup.py 2019-07-01 18:40:58 +02:00
Florent Kermarrec
fa8935f4ea add travis-ci 2019-06-24 12:41:33 +02:00
Florent Kermarrec
325b6399a2 add test/test_targets (only test platforms with simple target for now) 2019-06-24 12:38:58 +02:00
Florent Kermarrec
aeddb93729 add copyright header to all files, udpate. 2019-06-24 12:13:54 +02:00
enjoy-digital
0b53b83ba9
Merge pull request #2 from xobs/add-fomu-target
Add fomu target
2019-06-20 07:07:04 +02:00
Sean Cross
49ffc94e85 partner: platforms: fomu_evt: rename rgb_led_n -> rgb_led
The evt platform has a different naming scheme from the other two
versions of Fomu.

This harmonises the naming of the rgb_led pads between all of the Fomu
variants.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 19:21:15 -07:00
Sean Cross
d01711fdf9 partner: targets: add fomu target
The `fomu` target represents a generic target that supports the Fomu
48 MHz crystal, with or without a PLL.

It does not yet include a BaseSoC, since that requires USB and
up5kspram, neither of which are present yet.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 12:58:13 -07:00
Sean Cross
2c0ed53354 gitignore: ignore temporary python files
These get generated whenever one of these boards are used, which can
cause issues when this repo is used as a submodule.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 12:51:06 -07:00
Florent Kermarrec
482a00aa76 fomu: move to right location 2019-06-12 19:50:46 +02:00
enjoy-digital
de78b12b53
Merge pull request #1 from TomKeddie/tomk_20190612_fomu_platform
Add fomu platform definitions
2019-06-12 19:47:42 +02:00
Tom Keddie
c87412b098 Review feedback - rename dvt to pvt - remove serial from both pvt and hacker - remove NC spi wp and hold pins from hacker - remove spiflash4x as pins are NC Added links to schematic/cad data 2019-06-12 05:09:43 -07:00
Tom Keddie
d9cf64b8b5 Update @mithro fomu platform defs from @xobs foboot and try to make them all match the litex style a little more 2019-06-12 05:09:43 -07:00
Tom Keddie
10fc74fc3e Add fomu platform defs from mithro 2019-06-12 05:09:43 -07:00
Florent Kermarrec
44d01edab9 dispatch platforms/targets by level of support 2019-06-10 18:59:49 +02:00
Florent Kermarrec
4213c75e48 init repo with litex official boards 2019-06-10 17:11:36 +02:00