11bf6ea703
targets/siglent_sds1104xe.py: added note on how to use crossover with jtagbone
2024-03-20 16:58:38 +01:00
6333fbe724
targets/siglent_sds1104xe: Update with new LiteX Ethernet/Etherbone integration.
2023-11-13 09:02:09 +01:00
1969b4f6d3
siglent_sds1104xe: Update Ethernet/Etherbone integration.
2023-11-10 18:58:42 +01:00
0d560bc240
targets/siglent_sds1104xe: Review.
2023-10-23 19:25:12 +02:00
26d112b094
targets/siglent_sds1104xe: simplify etherbone by using new etherbone's params to specify hybrid mode
2023-10-23 19:07:37 +02:00
d00810c983
sds1104xe: Fix typo.
2023-10-06 19:25:22 +02:00
f400179b5b
targets: Import all from litex.gen on all targets.
2023-02-23 09:09:33 +01:00
58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
16b9677acd
targets: Switch to soc_core_argdict.
...
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
877bc4b45e
targets: Use full imports (vendor_board).
2022-05-02 12:55:11 +02:00
4fbf2fc7de
targets: Replace self.add_wb_master with self.bus.add_master.
2022-04-21 15:32:19 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
00ff61baa9
targets: Simplify clock domains and remove useless reset_less.
...
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
df36cdbcc9
siglent_sds1104xe: Switch back to native DRAM width (now possible with Nax).
2022-02-18 11:47:08 +01:00
d85f88f42a
siglent_sds1104xe: Reduce DRAM's width to 16-bit for now (to use NaxRiscv).
2022-02-16 17:59:40 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
d92a2b82fb
targets/l2_cache_reverse: Now defaulting to False in LiteX, so setting it to False for correct Framebuffer operations is no longer required.
2022-01-18 11:37:55 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
9686db0ed3
targets: Update names in build descriptions.
2021-04-29 11:56:52 +02:00
6117b98049
siglent_sds1104xe: Avoid disabling hardware interface with BIOS ethernet reset.
2021-04-29 11:52:41 +02:00
c28a161392
siglent_sds1104xe: Expose ethphy (to allow correct .dts generation).
2021-04-29 11:02:13 +02:00
7d651a9a17
siglent_sds1104xe: Switch to VideoVGAPHY and adjust timings.
2021-04-29 10:41:19 +02:00
cfbcb8538d
siglent_sds1104xe: Use custom 800x480 video timings.
2021-04-28 16:59:09 +02:00
f7ee3fa454
sds1104xe: Framebuffer fixes.
2021-04-27 19:32:03 +02:00
1ca8ef97a1
targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
2021-03-29 16:03:19 +02:00
ba01776432
targets/add_sdram: Simplify call by removing useless arguments.
...
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
2021-03-29 15:28:31 +02:00
87df45e625
siglent_sds1104xe: Allow build without Etherbone.
2021-03-26 23:25:42 +01:00
c6ced293d4
targets/siglent_sds1104xe: Integrate VideoTerminal/VideoFrameBuffer.
2021-03-26 22:55:25 +01:00
062b899e29
platforms/targets: Add mode Vendor prefixes.
2021-03-25 16:19:11 +01:00
Gwenhael Goavec-Merou
Florent Kermarrec
Gwenhael Goavec-Merou