Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,313 Commits 9 Branches 14 Tags 12 MiB
Commit Graph

755 Commits

Author SHA1 Message Date
Florent Kermarrec db9173ad8b targets/alchitry_mojo: Fix build. 2022-01-05 18:11:53 +01:00
Florent Kermarrec 53dc00eab7 targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description. 
Also do minor adjustments while doing this.
 2022-01-05 17:06:40 +01:00
Florent Kermarrec c836b57145 titanium_ti60_f225_dev_kit: Add HyperRAM separator. 2022-01-04 15:18:26 +01:00
Florent Kermarrec 28a6fad705 targets/efinix_titanium_ti60_f225: Defaults to 200MHz clock and increase HyperRam size to 32MB. 2022-01-04 11:25:18 +01:00
Primesh f5ac5200ff
Added Spartan Edge Accelerator board 2022-01-03 17:14:54 -05:00
Primesh 713ae531f6 Add Spartan Edge Accelerator support 2022-01-03 16:31:13 -05:00
enjoy-digital 059563245d
Merge pull request #314 from sergachev/zedboard 
LiteX BIOS on Zedboard
 2022-01-03 17:59:22 +01:00
Florent Kermarrec c9816f2bc1 snicker_doodle: Add z7-10/z7-20 variants support. 2022-01-03 17:15:27 +01:00
Florent Kermarrec dc61d383e6 snickerdoodle: Rename to krtkl_snicker_doodle and do minor cosmetic changes. 2022-01-03 17:09:17 +01:00
Derek Mulcahy a118a0e499 Replaced Blinky with LedChaser. 2021-12-24 22:14:18 -05:00
Ilia Sergachev bc3c42ab5f zedboard: disable soc uart for all variants (zynq does not need it, for soft cpus there are no pins) 2021-12-22 03:28:13 +01:00
Ilia Sergachev 53ce00b3fd zedboard: add target with bios on arm zynq cpu 2021-12-22 03:14:13 +01:00
Derek Mulcahy 154cb672da Removed unused ext_freq parameter. 2021-12-20 21:42:21 -05:00
Derek Mulcahy 81404ff185 Improved PS7 support. Configured external clock. 2021-12-20 21:14:18 -05:00
derekmulcahy d64207f8b6
Merge branch 'litex-hub:master' into master 2021-12-20 17:35:35 -05:00
enjoy-digital 94b4789286
Merge pull request #312 from trabucayre/arty_z7 
adding digilent_arty_z7 support
 2021-12-20 21:50:41 +01:00
enjoy-digital 8772190177
Merge pull request #311 from tilk/icesugar_pro 
Option --with-spi-flash for iCESugar-Pro
 2021-12-20 21:49:26 +01:00
Florent Kermarrec 8664b59f23 targets: Fix --bios-flash-offset support and other minor cleanups. 2021-12-20 21:41:12 +01:00
enjoy-digital c6303480cb
Merge pull request #308 from hubmartin/tinyfpga_bx 
Fix bios-flash-offset for tinyFPGA
 2021-12-20 21:29:37 +01:00
Gwenhael Goavec-Merou bb92bb00a8 adding digilent_arty_z7 support 2021-12-20 18:02:57 +01:00
derekmulcahy 4c76e12932
Merge branch 'litex-hub:master' into master 2021-12-20 10:54:09 -05:00
Marek Materzok 7fb225a162 Option --with-spi-flash for iCESugar-Pro 2021-12-19 15:50:52 +01:00
Franck Jullien f18c1a033c Efinix: ti60: add HyperRAM support 2021-12-17 10:23:10 +01:00
Derek Mulcahy 1c87c391c4 Initial release for Snickerdoodle 2021-12-14 16:00:42 -05:00
hubmartin 84f267e00c Change bios-flash-offset for tinyFPGA 2021-12-14 19:10:03 +01:00
enjoy-digital c2a840f777
Merge pull request #307 from fjullien/titanium_spi 
Titanium spi
 2021-12-14 08:21:15 +01:00
Franck Jullien 9608cae2ee efinix: Ti60f225 change spi_flash module 2021-12-13 23:01:48 +01:00
Franck Jullien be7dbf3b1b exfinix: efinix_titanium_ti60_f225_dev_kit: fix typo 2021-12-13 22:53:50 +01:00
Florent Kermarrec 179e9090d1 Rename efinix_titanium_ti60_bga225_dev_kit to efinix_titanium_ti60_f225_dev_kit and also exclude it from tested platforms/targets. 2021-12-13 15:54:56 +01:00
Franck Jullien e84f32b918 efinix: add titanium Ti60 dev kit 2021-12-13 09:37:14 +01:00
enjoy-digital 35e0026875
Merge pull request #303 from sergachev/master 
sipeed_tang_nano_4k: add option to build with Gowin EMCU
 2021-12-09 14:30:54 +01:00
Ilia Sergachev 14a8c50e97 sipeed_tang_nano_4k: connect Gowin EMCU UART, undo unnecessary changes 2021-12-09 00:17:48 +01:00
Ilia Sergachev 6274c4c425 sipeed_tang_nano_4k: connect Gowin EMCU UART 2021-12-09 00:12:31 +01:00
Ilia Sergachev 13c83ba532 sipeed_tang_nano_4k: add initial Gowin EMCU support 2021-12-08 23:50:14 +01:00
Ilia Sergachev 4287ab561e sipeed_tang_nano_4k: allow non-vexriscv CPUs 2021-12-08 23:33:49 +01:00
enjoy-digital 9119250276
Merge pull request #300 from tilk/de1_soc 
Better support for DE1-SoC
 2021-12-08 06:18:25 +01:00
enjoy-digital 2b7587632f
Merge pull request #299 from gregdavill/butterstick-updates 
Butterstick updates
 2021-12-08 06:16:29 +01:00
Florent Kermarrec 8ad89881c2 fairwaves_xtrx: Add pcie_x2 definitions and switch to it. 2021-12-07 15:27:55 +01:00
Marek Materzok cbeb2a3792 Add LedChaser to DE1-SoC 2021-12-05 20:16:10 +01:00
Greg Davill fd2ec534a7 butterstick: Add extra pins 2021-12-05 20:33:28 +10:30
Greg Davill c8a8e943b5 butterstick: add --sdram-device option 
Set 64M16 as default sdram-device.

Related to #298
 2021-12-04 17:07:06 +10:30
Florent Kermarrec bf8b23c19f trenz_tec0117: Update target. 2021-12-02 18:23:11 +01:00
enjoy-digital efa1f46356
Merge pull request #297 from sergachev/master 
Fix Sipeed Tang Nano 4k example compilation; adapt Gowin PLL class changes
 2021-12-02 09:14:32 +01:00
Ilia Sergachev 666ef9dad3 sipeed_tang_nano_4k: use minimal vexriscv variant to fit into number of BSRAMs 2021-11-29 11:46:32 +01:00
Ilia Sergachev 2fb734a0f2 sipeed_tang_nano*: adapt Gowin PLL changes in litex 2021-11-29 11:45:13 +01:00
Florent Kermarrec 1829693877 fairwaves_xtrx: Integrate ICAP/SPIFlash (for update over PCIe). 2021-11-26 16:18:52 +01:00
enjoy-digital fe14e16c1b
Merge branch 'master' into tang_primer 2021-11-23 19:04:09 +01:00
Miodrag Milanovic 6954dd25eb Set minimal core, since full does not work for some reason 2021-11-23 15:26:54 +01:00
Miodrag Milanovic 0b7fabb864 FireAnt board support 2021-11-23 14:43:52 +01:00
Miodrag Milanovic 2cc322e65d Add initial support for Tang Primer board 2021-11-22 19:10:11 +01:00
Florent Kermarrec 70c0dbb185 targets/radiona_ulx3s: Remove SDRAM underflows debug pin. 2021-11-22 11:54:18 +01:00
Florent Kermarrec 60b769b624 efinix_trion_t120_bga576_dev_kit/ethernet: Disable software debug (RX now seems to be working fine). 2021-11-16 18:53:15 +01:00
Florent Kermarrec 996f5b2edd efinix_trion_t120_bga576_dev_kit: Enable target1 port and also connect it to SoC. 2021-11-16 18:12:42 +01:00
Florent Kermarrec 7ce6c4cf79 efinix_trion_t120_bga576_dev_kit: Switch to ctrl_type = "none" (Also seems to work fine, avoid ddr_reset_sequencer dependency). 2021-11-16 17:50:47 +01:00
Florent Kermarrec 99f4f97f00 efinix_trion_t120_bga576_dev_kit: Use new InterfaceWriterBlock/InterfaceWriterXMLBlock and move PLL/DRAM blocks definition to target. 2021-11-16 17:41:26 +01:00
Hans Baier e16fa193fc qmtech 10cl006: remove all options which won't fit into the device. use uartbone as default 2021-11-15 10:23:01 +07:00
Florent Kermarrec 138dc1467e quicklogic_quickfeather: Fix build with GPIOIn when cpu-type=None (IRQ not supported). 2021-11-14 09:30:52 +01:00
Florent Kermarrec ed67b91fcc quicklogic_quickfeather: Simplify cpu_type switch between None/EOS-S3. 2021-11-14 09:26:29 +01:00
Florent Kermarrec 2d3422869c quicklogic_quickfeather: Update clocking. 2021-11-14 09:19:19 +01:00
Florent Kermarrec df468fcf85 quicklogic_quickfeather: Avoid add_csr calls (not required). 2021-11-14 08:54:49 +01:00
Florent Kermarrec 06bae58f48 efinix_trion_t120_bga576: Do a bit a of cleanup on LPDDR3 now that working. 2021-11-12 19:43:28 +01:00
Florent Kermarrec 86f6d7e66b efinix_trion_t120_bga576_dev_kit: Remove test command. 2021-11-12 18:06:11 +01:00
Florent Kermarrec 4e03f66fad efinix_trion_t120_bga576_dev_kit: Remove debug, integrate LPDDR3 as done on other targets. 
Also lower sys_clk_freq since seems to cause issue with DRAM at 100MHz: Needs to be investigated.
 2021-11-12 18:04:30 +01:00
Florent Kermarrec 77fffda9cd efinix_trion_t120_bga576_dev_kit: Switch to UARTBone, Add LiteScope on Pseudo-AXI, fix addressing and do first successful LPDDR3 accesses :) 2021-11-12 16:41:42 +01:00
Gwenhael Goavec-Merou 648d38da7e quicklogic_quickfeather: add button and GPIOIn 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 2021-11-12 13:21:00 +01:00
Florent Kermarrec b6c5a85b98 Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash. 
Tested with:
./efinix_trion_t20_mipi_dev_kit.py --with-spi-flash --build --load
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov 12 2021 08:37:48
 BIOS CRC passed (2bec12a3)

 Migen git sha1: 7507a2b
 LiteX git sha1: f679992f

--=============== SoC ==================--
CPU:		VexRiscv @ 100MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32JV SPI Flash @0x00400000...
Enabling Quad mode...
First SPI Flash block erased, unable to perform freq test.
Memspeed at 0x400000 (Sequential, 4.0KiB)...
   Read speed: 2.6MiB/s
Memspeed at 0x400000 (Random, 4.0KiB)...
   Read speed: 1.5MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2021-11-12 08:42:10 +01:00
Florent Kermarrec d6fc4b412e efinix_trion_t120/t20_dev_kit: Switch back to 100MHz (now that timings constraints are correctly applied). 2021-11-12 07:58:51 +01:00
Florent Kermarrec 7ce8567d9b targets/efinix: Bitstreams now directly generated to gateware directory. 2021-11-11 11:19:39 +01:00
Florent Kermarrec 855fd7e3d7 efinix_trion_t120_bga576_dev_kit: Continue LPDDR3 integration... 2021-11-10 19:40:35 +01:00
Florent Kermarrec 224f527baa efinix_trion_t120_bga576_dev_kit: Go a bit further in DRAM integration. 2021-11-10 12:07:30 +01:00
Gwenhael Goavec-Merou 040e7b3104 quicklogic_quickfeather: Use initial EOS-S3 support/integration. 2021-11-09 18:59:37 +01:00
Florent Kermarrec 8ce83ce92f efinix_trion_t120_bga576_dev_kit: Add inital LPDDR3 integration (not yet working). 2021-11-09 16:13:40 +01:00
Florent Kermarrec 9a7e5f40b4 efinix_trion_t120_bga576_dev_kit: Add Ethernet/Etherbone support. 
Still not fully validated: TX seems OK but RX seems shifted/corrupted.
 2021-11-09 11:32:32 +01:00
Florent Kermarrec ccebae6f55 targets/hyperram: Update integration. 2021-11-08 16:39:49 +01:00
Florent Kermarrec 184f41e61a sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds). 
Working correctly on hardware with updated CH552 firmware & patched litex_server...
 2021-11-08 09:23:44 +01:00
Hans Baier d6bf2fd00e terasic_sockit: Use standard SDRAM module from litedram 2021-11-08 12:48:03 +07:00
Hans Baier a9847f15a7 qmtech_5cefa2: tuned the clock phase shift to be able to run the system at 105MHz 2021-11-06 09:58:10 +07:00
Hans Baier b2813cfb70 use the right DRAM chip for the QMTech Altera boards 2021-11-06 08:45:03 +07:00
Florent Kermarrec 6e7c76b71e fairwaves_xtrx: Add clk60 (from USB PHY) as default Clk when no PCIe. 
Fixes CI.
 2021-11-05 15:22:55 +01:00
Florent Kermarrec ceaaf67dfd Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1). 2021-11-05 14:52:45 +01:00
enjoy-digital 01463a81a4
Merge pull request #287 from hansfbaier/qmtech-fixes 
10cl006: add missing spiflash option
 2021-11-05 07:11:27 +01:00
Hans Baier 3a25af1c28 10cl006: add missing spiflash option 2021-11-05 09:57:04 +07:00
Hans Baier 0edce3a176 Add support for QMTech 5CEFA2 board (Cyclone V) 2021-11-05 09:53:25 +07:00
Florent Kermarrec a482d7f6de targets/qmtech_xc7a35t: Use gpio_serial as serial when not mounted on daughterboard. 2021-11-04 18:52:36 +01:00
Florent Kermarrec 9543b5efae marble/marble_mini: Add berkeleylab prefix. 2021-11-04 18:42:16 +01:00
Florent Kermarrec 5e5ae880a4 targets/litex_acorn_baseboard: Integrate WS2812/NeoPixel. 
Tested with:
./litex_acorn_baseboard.py --cpu-type=None --uart-name=uartbone --with-ws2812 --build --csr-csv=csr.csv --load
litex_server --uart --uart-port=/dev/ttyUSBX
And test script: https://gist.github.com/enjoy-digital/c32c679a9ee4429d7f38a5ca5016a45a
 2021-11-04 16:36:25 +01:00
enjoy-digital 808befec3b
Merge pull request #283 from yetifrisstlama/master 
add Marble-board platform and target file
 2021-11-04 15:20:11 +01:00
Hans Baier 7aa639ac0f QMTech boards: fix swapped RX/TX lines, remove double uart replacer 2021-11-02 09:34:25 +07:00
Michael Betz e645eb243b add marble board platform and target file 2021-10-28 18:41:22 +02:00
Florent Kermarrec 207afb98fc ego1: Switch to VideoTerminal (LiteVideo is no longer provided by default with LiteX). 2021-10-27 16:29:46 +02:00
Florent Kermarrec 91818bc5f0 targets/gsd_butterstick/BaseSoC: Set default device to 85F (consistency with default arguments). 2021-10-26 17:01:55 +02:00
Florent Kermarrec c7a91f9eab efinix: Enable identifier on SoC (issue fixed in LiteX). 2021-10-25 19:33:49 +02:00
Florent Kermarrec 4bcfde8882 efinix: Avoid no_we on ROM/RAMs (no longer required). 2021-10-25 19:10:03 +02:00
Florent Kermarrec d13a8d54b8 efinix_trion_txy_dev_kit: Lower sys_clk_freq for now to 50MHz, enable QSPI on T120 BGA576 dev kit. 
Now possible with recent LiteX changes to support Tristate IOs.
 2021-10-25 18:35:35 +02:00
Florent Kermarrec f230eaf9bc efinix_trion_t120_bga576: Add Tristate test code. 2021-10-25 15:01:34 +02:00
Florent Kermarrec 0ac0f9e75d efinix_xyloni_dev_kit: Switch to openFPGALoader to load bitstream. 2021-10-25 12:49:48 +02:00
Florent Kermarrec fc05379929 efinix_xyloni_dev_kit: Use PLL. 2021-10-25 12:16:47 +02:00
Florent Kermarrec 394ea23b99 efinix_xyloni_dev_kit: Only force variant to minimal for Vexriscv. 2021-10-22 14:47:12 +02:00
Florent Kermarrec 75fd276dbe efinix_xyloni_dev_kit: Increase similarities with others boards and make target very similar to iceBreaker/Fomu/TangNano4k. 2021-10-21 11:34:55 +02:00
Florent Kermarrec dc1328f1a5 efinix_xyloni_dev_kit: Fix copyrights. 2021-10-21 10:12:46 +02:00