f50ee97520
alinx_axau15: Minor adjustments.
2024-03-14 15:13:59 +01:00
e980798437
gsd_orangecrab: Add --without_dfu_rst argument to allow disabling reset to DFU on Button press.
...
This is useful in some case where were button input is force through hardware change to force DFU to be in reset at startup.
2024-03-11 17:23:42 +01:00
45fddf0c3c
Merge pull request #1 from skrutt/VGA-connector-pinout
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Correct pinout for VGA connector
2024-03-08 10:57:36 +01:00
0ec5624875
Correct pinout for VGA connector
2024-03-08 10:22:32 +01:00
91aff9816d
targets/litex_acorn_baseboard_mini: Add with_dram parameter to allow build without DRAM.
2024-03-07 18:30:18 +01:00
8ce88ee51e
Merge pull request #569 from trabucayre/olimex_gatemate_a1_evb
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Olimex gatemate a1 evb
2024-03-05 09:38:03 +01:00
0b5727692f
litex_acorn_baseboard_mini: Fix imports.
2024-03-04 13:22:41 +01:00
214b1505a6
README: Adding colognechip GateMate EVB
2024-03-02 12:23:41 +01:00
e1e989acac
Olimex GateMate A1 EVB: new Board
2024-03-02 12:23:27 +01:00
85971de42e
Merge pull request #568 from hansfbaier/qmteck-k325-fix
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Enable bitstream compression on Kintex K325T
2024-03-02 10:42:20 +01:00
e5d8f62c83
enable bitstream compression on Kintex K325T
2024-03-02 07:48:12 +07:00
8b80cc1c3a
litex_acorn_baseboard_mini: Add SATA support (Gen1 and Gen2).
2024-02-29 14:36:51 +01:00
9dd246c26e
Merge pull request #567 from trabucayre/gatemate_evb
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adding colognechip_gatemate_evb
2024-02-28 17:35:48 +01:00
fab6bcf514
Merge pull request #566 from hansfbaier/qmteck-k325-fix
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Qmtech k325: fix wrong button assignment
2024-02-28 17:35:04 +01:00
af09c81db6
adding colognechip_gatemate_evb
2024-02-28 17:27:21 +01:00
82c0e191a7
QMTech XC7K325T: use the buttons on the core board
2024-02-28 04:40:17 +07:00
33a0975dd7
litex_acorn_baseboard_mini: Allow configurable sys_clk_freq with Ethernet/Etherbone.
2024-02-27 12:38:08 +01:00
72ea25512b
QMTech XC7K325T: remove wrong reset button assignment
2024-02-27 15:42:38 +07:00
7bc03e5fbc
targets/litex_acorn_baseboard_mini: Make it similar to other targets and keep SoC + UART + DRAM + Ethernet.
2024-02-26 17:29:09 +01:00
aa34acc426
targets/digilent_arty: Allow --with-ethernet and --with-etherbone and remove --with-hybrid.
2024-02-26 15:56:58 +01:00
feae57e7fb
target/qmtech_kintex7_devboard: +X.
2024-02-26 15:41:09 +01:00
23313de1b4
targets: Add initial litex_acorn_baseboard_mini target from acorn_baseboard repository.
2024-02-26 12:25:15 +01:00
6d07eda3c0
targets/digilent_arty: Fix indent on with_usb.
2024-02-21 10:06:49 +01:00
68e0453677
targets/digilent_arty: Move USB integrated to BaseSoC.
2024-02-21 09:03:53 +01:00
8242ab3974
targets/digilent_arty: Add Ethernet/Etherbone Hybrid mode + USB-Host (through Machyne PMOD).
2024-02-20 19:44:10 +01:00
9c3f272f6e
platforms/lambdaconcept_ecpix5: Minor cleanup.
2024-02-09 12:20:12 +01:00
f7c7a5a7e5
Merge pull request #563 from smunaut/adi
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Some minor updates to the ADI ADRV2CRR board
2024-02-06 16:33:53 +01:00
a6f8f0e696
Merge pull request #561 from ruurdk/qmtech
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Add support for QMTech Kintex 7 Development board
2024-02-06 16:29:54 +01:00
24fc3d48a4
Merge pull request #560 from Johnsel/axau15_update
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AXAU15: Updated FMC+ pinout
2024-02-06 16:28:36 +01:00
b3caabcca3
di_adrv2crr_fmc: Bump PCIe to 8 lanes
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There used to be an issue with 8 lanes litepcie USP for that board
when it was first added, but it's been solved now, so might as well
use all the available lanes
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2024-02-05 11:43:02 +01:00
2264df8a0a
adi_adrv2crr_fmc: Speedgrade of the PLL is -2
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Speedgrade of the chip was updated in a previous commit, but
I forgot to update the PLL too
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2024-02-05 11:42:14 +01:00
4d967e8387
add to boards list
2024-02-01 16:18:26 +01:00
66152390ba
Add support for QMTech Kintex 7 Development board
2024-02-01 16:16:01 +01:00
741082e5ee
Merge branch 'litex-hub:master' into axau15_update
2024-01-27 03:28:28 +01:00
721fa0b4b3
axau15: added more FMC+ pins and made some corrrections
2024-01-27 03:27:48 +01:00
39dc0b36a4
sipeed_tang_mega_138k: Fix build with ethernet and local/remote ip indent.
2024-01-22 13:20:07 +01:00
dbcd5bc3f5
Merge pull request #559 from racerxdl/master
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sipeed_tang_mega_138k: Added PCIe reset and other pins from sipeed dock
2024-01-15 08:42:37 +01:00
261c61cf62
targets/sipeed_tang_nano_4k: Remove commited spiflash.o.
2024-01-14 11:24:18 +01:00
3438f74224
sipeed_tang_mega_138k: Added PCIe reset and other pins from sipeed documentation
2024-01-13 04:38:54 -03:00
926d54cb41
sipeed_tang_nano_4k: Switch to LiteX's UART and expose hyperram parameter.
2024-01-11 13:54:44 +01:00
688a020f35
sipeed_tang_meta_138k: Add gowin_ae350 CPU initial support.
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./sipeed_tang_mega_138k.py --cpu-type=gowin_ae350 --build --flash
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2024 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Jan 11 2024 12:37:50
BIOS CRC passed (0efaefbe)
LiteX git sha1: e689aab1
--=============== SoC ==================--
CPU: Gowin AE350 @ 800MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128.0KiB
SRAM: 8.0KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on Tang Mega 138K 2024-01-11 12:37:47
2024-01-11 13:17:05 +01:00
29143a89f8
platforms/sipeed_tang_mega_138k: adding some resources/connectors definition (SPI flash, Buttons, SDRAM connector)
2024-01-10 10:37:01 +01:00
52f9f0f107
Merge pull request #555 from machdyne/master
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add support for minze board
2024-01-07 08:10:51 +01:00
52aeec00d7
sipeed_tang_nano_4k: Remove note since openFPGALoader regression has been fixed.
2024-01-04 18:29:31 +01:00
c0a98a6b9d
targets/sipeed_tang_nano_4k: Directly integrate flashing of EMCU flash.
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Ex to build/flash bitstream + firmware with EMCU:
./sipeed_tang_nano_4k.py --cpu-type=gowin_emcu --build --flash
2024-01-03 13:07:44 +01:00
55ade3b2df
sipeed_tang_nano_4k: Minor cleanup/add comments.
2024-01-02 13:42:56 +01:00
e585d786e9
setup.py: Add classifiers.
2024-01-01 15:31:42 +01:00
fd59d954ba
add support for minze board
2023-12-29 06:01:59 +01:00
982038508e
alinx_axau15/PCIe: Switch to Gen3/128-bit for now (configuration used on others Ultrascale+ Gen3 X4 boards).
2023-12-28 19:56:52 +01:00
e229d1a0b6
alinx_axau15: First review/cleanup pass and fix missing INTERNAL_VREF on bank 66.
2023-12-28 19:48:50 +01:00
Florent Kermarrec
skrutt
Gwenhael Goavec-Merou
Hans Baier
Gwenhael Goavec-Merou
Sylvain Munaut
Ruurd Keizer
John Simons
Lucas Teske
inc