070c4cd387
cores/cpu/vexiiriscv: Add PMP support
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The RISC-V PMP feature can now be enabled via --vexii-args="--pmp-size=8" for instance.
TOR support can be disabled via --pmp-tor-disable to save area / timings
2024-11-26 17:40:03 +01:00
29c5a1db83
build/altera/quartus: Add .svf generation (required for now with openFPGALoader) and create_rbf property.
2024-11-26 16:11:38 +01:00
10dcc73676
Merge pull request #2125 from trabucayre/ecp5_diamond_tristate
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build/lattice/common.py: added Tristate support for ECP5 when build with diamond
2024-11-18 12:40:24 +01:00
52148c7aad
soc/integration/soc_core: Fix with_uartbone changes.
2024-11-18 11:07:51 +01:00
211ce59df4
build/lattice/common.py: added Tristate support for ECP5 when build with diamond
2024-11-17 11:32:33 +01:00
8041969e00
Merge pull request #2100 from VOGL-electronic/efinix_io_optimize
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efinix: gpio: use constant output option
2024-11-15 09:38:50 +01:00
8399c919bd
Merge pull request #2122 from acceleratedtech/accelerated/uart-dynamic-baudrate-for-upstream
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feat: add uart_with_dynamic_baudrate to SoCCore
2024-11-15 09:36:20 +01:00
2b3fd723a2
Merge pull request #2101 from VOGL-electronic/bios_spi_fix
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bios: litespi: clear rx queue after write Beta
2024-11-13 11:12:51 +01:00
0f45ea221e
Merge pull request #2119 from long-pham/pr_useAllCPUCores
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Utilizing all available CPU cores in the software make cmd
2024-11-12 21:45:07 +01:00
e9e0140c74
Merge pull request #2118 from long-pham/pr_openfpgaloader
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Add FTDI serial number option to openfpgaloader
2024-11-12 21:40:57 +01:00
8ece14849a
Merge pull request #2117 from long-pham/main
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Use MMCME4_ADV in USPMMCM to enable finer-grained clock output ctrl
2024-11-12 21:40:25 +01:00
d7a8743f20
Merge pull request #2123 from trabucayre/vhd2vconverter_libraries
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build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.
2024-11-12 21:38:38 +01:00
f056f37c29
Merge pull request #2120 from juiceRv/fix/veril-fst-trace
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Fixes: Fix not close trace file when the sim is finished
2024-11-12 21:37:09 +01:00
f731b36c9b
build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.
2024-11-09 07:55:18 +01:00
f53178d712
feat: add uart_with_dynamic_baudrate to SoCCore
2024-11-08 18:49:01 -05:00
5fa144ec3a
Fixes: Fix no close trace file when the sim is finished
2024-11-07 14:41:26 +08:00
9cc8bf9866
Switch to using MMCME4_ADV in USPMMCM to enable finer-grained clock output control
2024-11-06 13:48:56 -08:00
8b4949edcd
Merge pull request #2115 from CKeilbar/soc-region-check-fix
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Fix SOC region range check
2024-11-06 22:29:05 +01:00
de9d3ab314
soc/cores/cpu/urv: Add DataBusToWishbone and use it.
2024-11-06 21:59:11 +01:00
2b3913982c
soc/cores/cpu/urv: Add InstructionBusToWishbone and use it.
2024-11-06 21:49:39 +01:00
d8e168a81f
Enhance software build performance by utilizing all available CPU cores in the builder
2024-11-06 11:35:28 -08:00
935326e66c
Add FTDI serial number option to openfpgaloader, useful when multiple similar boards are connected for CI/CD
2024-11-06 11:25:54 -08:00
1204cfda9d
soc/cores/cpu/urv: Fix add_sources.
2024-11-05 17:33:32 +01:00
20b0e98fe0
cpu/urv: Fix Instruction Bus conversion to Wishbone and only keep it now that working.
2024-11-05 17:19:13 +01:00
e9613499ea
Fix SOC region range check
2024-11-04 12:01:29 -08:00
0170462fe8
soc/cores/jtag: Fix/Test p_init/p_INIT workaround.
2024-11-04 14:34:28 +01:00
3f3249cdf0
Merge pull request #2113 from trabucayre/toolchain_diamond_sdc
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litex/build/lattice/diamond, platform: allows users to add custom sdc files
2024-11-04 12:53:48 +01:00
47e8b0273f
litex/build/lattice/diamond, platform: allows users to add custom sdc files
2024-11-04 12:42:38 +01:00
175e63ac4c
soc/cores/jtag: Add p_INIT/p_init workaround on ECP5JTAG to support Diamond and Trellis toolchains without manual changes.
2024-11-04 12:40:39 +01:00
4368d5a9ed
test/test_led: Comment out TestWS1812 test since seems broken, will need to be investigated/fixed.
2024-10-28 21:51:42 +01:00
61ab30a739
soc/cores/jtag: Revert p_INIT since not tested.
2024-10-28 20:05:47 +01:00
10184ad325
Merge pull request #2097 from trabucayre/build_diamond_addition
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Build diamond addition
2024-10-28 20:05:01 +01:00
23df960859
Merge pull request #2102 from Dolu1990/vexiiriscv-macsg
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Vexiiriscv update
2024-10-28 20:03:06 +01:00
dd092863f8
Merge branch 'master' into vexiiriscv-macsg
2024-10-28 20:02:56 +01:00
18714dfca3
Merge pull request #2104 from andelf/fix/ws2812-of-1-led
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Fixes #2103 : calculate memory depth for WS2812
2024-10-28 19:53:25 +01:00
59fc1caac4
Merge pull request #2099 from VOGL-electronic/vexiiriscv_sbi
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vexiiriscv: add options and conditions
2024-10-25 14:26:02 +02:00
773fb34079
vexiiriscv: have opensbi behind a option
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this way opensbi things are only activated,
when a linux variant is used.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-25 13:40:20 +02:00
8c7e510473
Fixes #2103 : calculate memory depth for WS2812
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See-also: https://github.com/m-labs/migen/pull/295
2024-10-25 11:48:57 +08:00
24db36ced5
Merge remote-tracking branch 'origin/master' into wuff
2024-10-24 16:02:52 +02:00
375940ad7d
soc/core/vexiiriscv: add macsg support (dma based ethernet)
2024-10-24 16:00:51 +02:00
d7bf75a75c
bios: litespi: add newline to debug output
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add newline to debug output
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-24 15:12:12 +02:00
63fa4fda85
bios: litespi: clear rx queue after write
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clear rx queue at the end of spiflash_master_write().
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-24 15:10:37 +02:00
54973eb9cb
build: efinix: use constant output option
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use constant output option, when the output is a `Constant`
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 14:12:30 +02:00
2d96e99494
build: io: SDRTristate: move check
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check wraped signals instead of before.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 11:18:57 +02:00
70f4a349e5
efinix: ifacewriter: fix in output
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fix in OUTPUT
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 11:10:16 +02:00
d6eec8e76d
efinix: ifacewriter: gpio: share common code
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share common code for INPUT, INOUT and OUTPUT.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 11:08:58 +02:00
c1225736a8
Merge pull request #2098 from enjoy-digital/urv
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Add initial uRV CPU support.
2024-10-17 19:45:44 +02:00
5f463dba87
CHANGES.md: Update.
2024-10-17 17:45:50 +02:00
aab8912f5a
soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU.
2024-10-17 17:44:40 +02:00
9449d25911
soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory.
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- Replace im bus wishbone adaptation with synchronous memory (for now and initial tests).
- Correctly handle dm bus wishbone adaptation (Added FIFO).
2024-10-17 16:54:20 +02:00
Dolu1990
Florent Kermarrec
Gwenhael Goavec-Merou
Jamey Hicks
Li.XiongHui
Long Pham
Chris Keilbart
Gwenhael Goavec-Merou
Fin Maaß
Andelf