Sebastien Bourdeauducq
|
6f99241585
|
Move Token to migen.flow.transactions
|
2012-12-14 15:55:38 +01:00 |
Sebastien Bourdeauducq
|
c44ff8941c
|
Move Token
|
2012-12-14 15:54:16 +01:00 |
Sebastien Bourdeauducq
|
3986790621
|
Remove ActorNode
|
2012-12-12 22:52:55 +01:00 |
Sebastien Bourdeauducq
|
28b4d99d31
|
replace some forgotten is_abstract()
|
2012-12-12 22:36:45 +01:00 |
Sebastien Bourdeauducq
|
a7227d7d2b
|
Remove ActorNode
|
2012-12-12 22:20:48 +01:00 |
Sebastien Bourdeauducq
|
8163ed4828
|
Merge branch 'master' of github.com:milkymist/migen
|
2012-12-06 20:57:30 +01:00 |
Sebastien Bourdeauducq
|
053f8ed82c
|
Fix instantiations
|
2012-12-06 20:57:00 +01:00 |
Sebastien Bourdeauducq
|
483b821342
|
fhdl/structure: do not create Signal in Instance when parameter is int
|
2012-12-06 20:56:46 +01:00 |
Sebastien Bourdeauducq
|
280a87ea69
|
elsewhere: do not create interface in default param
|
2012-12-06 17:34:48 +01:00 |
Sebastien Bourdeauducq
|
62187aa23d
|
migen/bank: do not create interface in default param
|
2012-12-06 17:28:28 +01:00 |
Sebastien Bourdeauducq
|
c3fdf42825
|
bus/csr: add SRAM
|
2012-12-06 17:16:17 +01:00 |
Sebastien Bourdeauducq
|
0392dd8ac2
|
bank/csrgen: interface -> bus
|
2012-12-06 17:15:47 +01:00 |
Sebastien Bourdeauducq
|
e89c66bf14
|
bank/csrgen: interface -> bus
|
2012-12-06 17:15:34 +01:00 |
Sebastien Bourdeauducq
|
273d9d285b
|
bank/description: define reset value of read signal
|
2012-12-05 16:40:44 +01:00 |
Sebastien Bourdeauducq
|
34ce934809
|
actorlib/sim: drive busy high until generator is finished
|
2012-12-05 16:40:12 +01:00 |
Sebastien Bourdeauducq
|
4bcb39699b
|
bus/wishbone/sram: accept memories < 32 bits
|
2012-12-01 13:04:22 +01:00 |
Sebastien Bourdeauducq
|
bec02c4783
|
Merge branch 'master' of github.com:milkymist/milkymist-ng
|
2012-12-01 12:59:47 +01:00 |
Sebastien Bourdeauducq
|
fee70e9866
|
Use Wishbone SRAM component from Migen
|
2012-12-01 12:59:32 +01:00 |
Sebastien Bourdeauducq
|
523816982a
|
bus/wishbone: add SRAM
|
2012-12-01 12:59:09 +01:00 |
Sebastien Bourdeauducq
|
adb1565d7a
|
pytholite: fix bit width of selection signal
|
2012-11-30 17:07:32 +01:00 |
Sebastien Bourdeauducq
|
cfb23c442f
|
pytholite: support signed registers
|
2012-11-30 17:07:12 +01:00 |
Michael Walle
|
7a1e4cb66b
|
lm32: fix watchpoints
The wp_match_n vector is off by one. Which results in undefined states, at
least in simulation.
Signed-off-by: Michael Walle <michael@walle.cc>
|
2012-11-30 15:22:40 +01:00 |
Sebastien Bourdeauducq
|
7093939309
|
corelogic/roundrobin: fix request width (again)
|
2012-11-29 23:47:51 +01:00 |
Sebastien Bourdeauducq
|
31c722f993
|
corelogic/roundrobin: fix request width
|
2012-11-29 23:47:08 +01:00 |
Sebastien Bourdeauducq
|
293a62dabe
|
Replace Signal(bits_for(... with Signal(max=...
|
2012-11-29 23:41:51 +01:00 |
Sebastien Bourdeauducq
|
8bf6945dfd
|
Use new bitwidth/signedness system
|
2012-11-29 23:38:04 +01:00 |
Sebastien Bourdeauducq
|
70e97e0456
|
Fix various errors from new bitwidth/signedness system conversion
|
2012-11-29 23:36:55 +01:00 |
Sebastien Bourdeauducq
|
261166d92b
|
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
|
2012-11-29 22:59:54 +01:00 |
Sebastien Bourdeauducq
|
55d143a454
|
fhdl/structure: add unary minus
|
2012-11-29 22:52:57 +01:00 |
Sebastien Bourdeauducq
|
d8e478efee
|
Replace Signal(bits_for(... with Signal(max=...
|
2012-11-29 21:53:36 +01:00 |
Sebastien Bourdeauducq
|
50ed73c937
|
New specification for width and signedness
|
2012-11-29 21:22:38 +01:00 |
Sebastien Bourdeauducq
|
6eebfce44a
|
Refactor Case
|
2012-11-29 01:11:15 +01:00 |
Sebastien Bourdeauducq
|
070652cc39
|
pytholite/reg: use source id in dictionary
|
2012-11-29 00:09:35 +01:00 |
Sebastien Bourdeauducq
|
7e2bc00c0a
|
Remove Constant
|
2012-11-28 23:18:53 +01:00 |
Sebastien Bourdeauducq
|
fee22a4631
|
Remove Constant
|
2012-11-28 23:18:43 +01:00 |
Sebastien Bourdeauducq
|
79e5f24a65
|
Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.
|
2012-11-28 22:49:22 +01:00 |
Sebastien Bourdeauducq
|
2a3ef28041
|
examples/sim/dataflow: update to new APIs
|
2012-11-28 22:44:14 +01:00 |
Sebastien Bourdeauducq
|
39d577d65e
|
examples/dataflow/dma: update to new APIs
|
2012-11-28 22:42:01 +01:00 |
Sebastien Bourdeauducq
|
7c4b5931bc
|
examples/basic: remove unroll example
|
2012-11-28 22:16:02 +01:00 |
Sebastien Bourdeauducq
|
59831e0485
|
fhdl/structure: improved bits_for function
|
2012-11-28 18:39:44 +01:00 |
Sebastien Bourdeauducq
|
11b1e53224
|
visit/NodeTransformer: copy most nodes
|
2012-11-28 17:50:55 +01:00 |
Sebastien Bourdeauducq
|
a2bcbfdf8f
|
fhdl/tools: use NodeTransformer to lower arrays
|
2012-11-28 17:46:15 +01:00 |
Sebastien Bourdeauducq
|
5440fa715c
|
examples/basic/arrays: add array assignment to fragment
|
2012-11-26 22:47:35 +01:00 |
Sebastien Bourdeauducq
|
3bc15024ac
|
fhdl/tools: use NodeVisitor
|
2012-11-26 21:40:23 +01:00 |
Sebastien Bourdeauducq
|
e3a983d731
|
Remove unroll
|
2012-11-26 20:07:48 +01:00 |
Sebastien Bourdeauducq
|
1460f069f6
|
fhdl/structure: remove deprecated MemoryPort
|
2012-11-26 19:36:43 +01:00 |
Sebastien Bourdeauducq
|
0620e75cb8
|
sram: do not use MemoryPort
|
2012-11-26 19:32:56 +01:00 |
Sebastien Bourdeauducq
|
5183774ec8
|
bus/wishbone2asmi: do not use MemoryPort
|
2012-11-26 19:14:59 +01:00 |
Sebastien Bourdeauducq
|
fc85ca53ad
|
actorlib/spi: do not use MemoryPort
|
2012-11-26 18:27:59 +01:00 |
Sebastien Bourdeauducq
|
0c29775a8f
|
tb/asmicon/asmicon_wb: more complete testing by default
|
2012-11-26 18:19:41 +01:00 |