9420aabc0d
sim: support arrays, and cat+slice in assignment target
2015-09-19 14:56:26 +08:00
ef92aa35f2
Merge branch 'master' of github.com:m-labs/migen
2015-09-19 12:22:47 +08:00
563231fdfb
migen/genlib/cdc: fix BusSynchronizer
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ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.
This fix add a timeout to detect such situation and create another token.
2015-09-19 12:21:54 +08:00
210ba91d58
migen/genlib/cdc: fix BusSynchronizer
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ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.
This fix add a timeout to detect such situation and create another token.
2015-09-19 12:18:39 +08:00
bfcc8f9661
sim: remove unneeded import
2015-09-19 12:18:20 +08:00
84f98b4632
genlib/CRG: fix variable name conflict
2015-09-19 11:18:44 +08:00
0a55ef5bc3
test: add divider
2015-09-18 11:07:14 +08:00
e4329c739c
actorlib/structuring: fix Pack in packetized mode
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Params need to be registered for the case when eop appears before the end of the pack cycle.
2015-09-18 02:28:02 +02:00
ec1d4edf84
sim: support Case
2015-09-17 17:25:06 +08:00
9d3fd50950
sim: variables are deprecated
2015-09-17 17:24:57 +08:00
2688d66ea1
sim: fix comb evaluation
2015-09-17 17:24:20 +08:00
049a8f082a
test/size: do not test removed functions
2015-09-17 17:23:19 +08:00
4a3a1bc5b0
test/coding: use new API
2015-09-17 17:22:59 +08:00
12cd390c0b
genlib/misc: add missing import
2015-09-17 17:22:44 +08:00
776579f0d7
fhdl/structure: all case statements should be lists
2015-09-17 17:22:24 +08:00
bcf62997f6
fhdl/bitcontainer: remove fiter
2015-09-17 17:22:03 +08:00
c2109f8f81
minor bugfixes
2015-09-17 15:20:27 +08:00
6e08df75ee
sim: support eval of slice, cat and mux
2015-09-17 14:39:36 +08:00
9dd3200ba2
fhdl/structure: fix namespace pollution
2015-09-17 14:39:17 +08:00
6569c516a1
test: bit reverse
2015-09-17 14:38:55 +08:00
0a92e346d3
fhdl/bitcontainer: remove fslice and freversed
2015-09-17 14:38:33 +08:00
fd88b9b8a3
test/constant: use new API
2015-09-17 11:08:40 +08:00
74c9159a01
add unittests for Constant
2015-09-17 11:06:04 +08:00
0b9c6720d8
doc: Constant
2015-09-17 11:05:57 +08:00
f5ab734bdf
fhdl/verilog: fix case value sort
2015-09-17 08:03:48 +08:00
e940c6d9b9
fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem
2015-09-15 12:38:02 +08:00
42afba2bbc
fhdl/decorators: remove traces of deprecated API
2015-09-12 19:44:35 +08:00
eb921fb957
genlib: remove reverse_bytes, FlipFlop, Counter
2015-09-12 19:40:29 +08:00
9667d61e84
genlib: cleanup CRG
2015-09-12 19:40:07 +08:00
1bdb9bee22
fhdl/decorators: remove deprecated API
2015-09-12 19:34:44 +08:00
336728413a
simplify imports, migen.fhdl.std -> migen
2015-09-12 19:34:07 +08:00
b43495aab1
build/xilinx: minor cleanup
2015-09-12 16:48:25 +08:00
047d1f48b5
test/support,signed,sort: use new simulator
2015-09-12 16:28:21 +08:00
8ee361ffe2
sim: refactor comb commit
2015-09-12 16:27:59 +08:00
5fa7f7414f
sim: support eval of nested lists
2015-09-12 16:01:53 +08:00
9556c335ea
genlib/sort: remove unneeded import
2015-09-12 15:21:42 +08:00
308c5d7a78
examples/graycounter: use new simulator
2015-09-12 15:14:21 +08:00
fa6d96bb9a
test/examples: do not attempt to run deleted examples
2015-09-12 15:13:45 +08:00
7bd72a16df
sim: support clock domains without sync
2015-09-12 15:12:57 +08:00
fd986210f8
simulator: support generators
2015-09-10 21:44:14 -07:00
10d89d81f4
new simulator: basic execution
2015-09-10 20:33:45 -07:00
49ef182305
fhdl/tools: add input lister
2015-09-10 20:33:10 -07:00
f9849fb8be
style
2015-09-10 20:32:47 -07:00
714ae43ab8
fhdl: remove features new simulator won't use
2015-09-10 18:29:57 -07:00
91ab3f0d01
remove genlib.misc.optree (use reduce instead)
2015-09-10 13:56:56 -07:00
31956de790
dvisampler/edid: fix sda sampling, needs to be similar to scl.
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Video sources with high scl frequency were not able to access EDID information through I2C.
I2C start was not detected correctly and was randomly reseting the fsm during transfers.(seen with litescope)
2015-09-10 20:51:10 +02:00
1dcd2ac1c0
fixed bug in value_bits_sign of mul operatiors
2015-09-10 10:53:26 -07:00
86f34e82c3
mibuild -> migen.build
2015-09-10 10:53:15 -07:00
07efe9d7b1
Merge pull request #31 from burnpanck/fix-value_bits_sign-mul
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fix bug in value_bits_sign of mul operatiors
2015-09-10 10:25:57 -07:00
b2c000e982
travis: only upload package when not building a pull request
2015-09-09 17:09:24 +02:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jordens
Yves Delley
Yann Sionneau