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Author	SHA1	Message	Date
Florent Kermarrec	0d58da0b57	tools/litex_sim: Cleanup ethernet local/ip address handling and do +1 when both ethernet/etherbone are enabled. ... Allow Etherbone to be by default at 192.168.1.50 when no Ethernet and 192.168.1.51 when also with Ethernet.	2025-01-03 21:57:29 +01:00
Florent Kermarrec	b9cc5c58d7	tools/litex_client/RemoteClient: Clear socket buffer in case of Timeout.	2025-01-03 16:37:56 +01:00
Florent Kermarrec	fc529dcab5	tools/litex_client/open: Reduce timeout now that error are handled.	2025-01-03 15:45:15 +01:00
Florent Kermarrec	1225bf4589	tools/litex_client/read: Handle errors by returning default values.	2025-01-03 15:44:41 +01:00
Florent Kermarrec	eec7733008	tools/remote/etherbone/EtherboneIPC/receive_packet: Return 0 in case of TimeoutError.	2025-01-03 15:43:03 +01:00
enjoy-digital	e3dcfbde60	Merge pull request #2153 from chmousset/add-ice40-diffinput ... [enh] Added differential input for ICE40	2025-01-03 08:13:33 +01:00
Charles-Henri Mousset	b36923914f	[enh] Added differential input for ICE40	2024-12-30 17:47:15 +01:00
enjoy-digital	05d7471f6c	Merge pull request #2147 from andelf/enhance/gowin-programmer ... build/gowin/programmer: refactor GowinProgrammer for enhanced functionality	2024-12-21 18:35:55 +01:00
enjoy-digital	263b1c393a	Merge pull request #2148 from dayjaby/backwards_compatibility_python3.7 ... backwards compatibility with python3.7	2024-12-21 18:34:44 +01:00
David Jablonski	3601b71584	backwards compatibility with python3.7	2024-12-21 14:33:28 +01:00
Andelf	3b19bcd583	build/gowin/programmer: refactor for enhanced functionality ... - Supports exflash - Use devname info for embflash or exflash - Allow customize operation mode via pmode	2024-12-21 03:53:09 +08:00
enjoy-digital	57333ee6c1	Merge pull request #2146 from FlyGoat/bus-width ... test: Include more bus option tests	2024-12-20 18:17:45 +01:00
Jiaxun Yang	1e21105731	test/test_integration: Add test for various bus options ... Test bus standard/data-width/address-width/interconnect combinations. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>	2024-12-20 12:22:39 +00:00
Jiaxun Yang	42b6d22428	test/test_integration: Derive from test_cpu ... Derive test_integration from test_cpu to prepare for other boot tests. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>	2024-12-20 12:22:39 +00:00
Gwenhael Goavec-Merou	8254a349f8	build/vhd2v_converter.py: fix params vs instance when conversion is disabled	2024-12-19 17:59:58 +01:00
enjoy-digital	6228d2b024	Merge pull request #2145 from trabucayre/litex_vhd2vconvert_instance ... build/vhd2v_converter: allows using an instance instead of entity_name + params	2024-12-19 16:51:09 +01:00
Gwenhael Goavec-Merou	a6845a7d63	build/vhd2v_converter: allows using an instance instead of entity_name + params	2024-12-19 15:20:50 +01:00
enjoy-digital	a6bdbedc07	Merge pull request #2139 from piotro888/pll-intel-reset ... cores/clock/intel: add reset to Intel PLLs	2024-12-18 14:52:21 +01:00
Piotr Wegrzyn	e18e2747f5	cores/clock/intel: add reset to Intel PLLs	2024-12-18 14:42:54 +01:00
enjoy-digital	1b47407aa0	Merge pull request #2143 from FlyGoat/csr-bridge-width ... soc/integration/soc: Fix CSRBridge Bus Width conversion	2024-12-18 14:35:42 +01:00
Jiaxun Yang	c52a2ca5df	soc/integration/soc: Fix CSRBridge Bus Width conversion ... Wishbone2CSR and AXILite2CSR bridges are incapable for performing bus width conversion, which means it's Bus slave port must have same width as CSRs. Use CSR width to create slave bus to allow width adaptar to be inserted by add_slave. Also add relevant assertion. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>	2024-12-18 10:29:33 +00:00
enjoy-digital	d05b6613e9	Merge pull request #2142 from andelf/fix/ws2812-led-count ... Fix WS2812 with nled=1	2024-12-17 19:33:39 +01:00
Andelf	f62ca50e95	soc/cores/led: fix ws2812 with nled=1	2024-12-18 01:01:25 +08:00
Florent Kermarrec	fdd7c97ce5	soc/cores/bitbang/i2c: Add connect_pads parameter.	2024-12-17 14:39:56 +01:00
enjoy-digital	c455a002d0	Merge pull request #2135 from enjoy-digital/Dolu1990-patch-3 ... Fix litex_setup.py OHCI clone	2024-12-15 12:26:12 +01:00
enjoy-digital	f63d4a8334	Merge pull request #2137 from trabucayre/xczu_special_overrides ... build/xilinx/platform: added xilinx_us_special_overrides for xczu devices	2024-12-12 15:29:14 +01:00
Gwenhael Goavec-Merou	95e76406e2	build/xilinx/platform: added xilinx_us_special_overrides for xczu devices	2024-12-12 11:46:48 +01:00
Dolu1990	d55d07ecdb	Fix litex_setup.py OHCI clone ... It wasn't recursive ^^	2024-12-11 12:05:56 +01:00
enjoy-digital	a32096e806	Merge pull request #2068 from VOGL-electronic/ddrtristate_oe2_optional ... build: io: make oe2 of DDRTristate optional	2024-12-04 09:17:02 +01:00
enjoy-digital	bff25c2d61	Merge pull request #2128 from VOGL-electronic/efinix-seu ... Add efinix SEU interface	2024-12-04 09:16:12 +01:00
enjoy-digital	9551845ee8	Merge pull request #2130 from enjoy-digital/Dolu1990-patch-2 ... cores/cpu/vexiiriscv: Add PMP support	2024-12-04 09:15:39 +01:00
enjoy-digital	4d748b7163	Merge pull request #2129 from VOGL-electronic/liblitespi-4k-erase ... liblitespi: add 4k erase function	2024-12-04 09:14:29 +01:00
enjoy-digital	e61196b1c9	Merge pull request #2131 from awaittrot/fix-spiram ... liblitespi: fix typo	2024-12-04 09:13:13 +01:00
Florent Kermarrec	ec06bf5955	build/xilinx/vivado: Allow passing str to add_false_path_constraint to allow mising Signals and str and simplify design constraints.	2024-12-02 17:28:38 +01:00
Florent Kermarrec	4e775a7bd6	build/generic_toolchain/add_false_path: Only add keep attribute if from_/to are Signals.	2024-12-02 17:27:44 +01:00
Florent Kermarrec	42cf2ca5d0	gen/fhdl/namer: Return Non if sig is None.	2024-12-02 17:27:05 +01:00
Florent Kermarrec	0ae90a9653	build/xilinx/vivado: Add/Improve comments to _build_clock_constraints/_build_false_path_constraints.	2024-12-02 16:39:07 +01:00
Florent Kermarrec	3ba9217122	build/xilinx/vivado: Move false path generation to _build_false_path_constraints.	2024-12-02 16:34:59 +01:00
Florent Kermarrec	30aeaf544a	build/vhd2v_converter: Create build_dir if not existing.	2024-11-28 13:33:29 +01:00
awaittrot	05dd84a5d6	liblitespi: fix typo	2024-11-27 22:18:24 +09:00
Gwenhael Goavec-Merou	76829aa6c9	Merge pull request #2127 from VOGL-electronic/efinity-path-fix ... Fix vdb path for Efinity 2024.2	2024-11-27 06:51:37 +01:00
Dolu1990	070c4cd387	cores/cpu/vexiiriscv: Add PMP support ... The RISC-V PMP feature can now be enabled via --vexii-args="--pmp-size=8" for instance. TOR support can be disabled via --pmp-tor-disable to save area / timings	2024-11-26 17:40:03 +01:00
Florent Kermarrec	29c5a1db83	build/altera/quartus: Add .svf generation (required for now with openFPGALoader) and create_rbf property.	2024-11-26 16:11:38 +01:00
Matthias Breithaupt	e91d4d1a39	Add efinix SEU interface ... Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>	2024-11-26 08:24:30 +01:00
Matthias Breithaupt	ed510bb9df	liblitespi: add 4k erase function ... Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>	2024-11-26 08:23:56 +01:00
Matthias Breithaupt	1ac1c83b51	Fix vdb path for Efinity 2024.2 ... With Efinity 2024.2, the path of the vdb file has changed from `work_syn` to `outflow`. To fix this, first check if the file exists in `work_syn`. If it doesn't `outflow` is used. Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>	2024-11-21 14:27:58 +01:00
enjoy-digital	10dcc73676	Merge pull request #2125 from trabucayre/ecp5_diamond_tristate ... build/lattice/common.py: added Tristate support for ECP5 when build with diamond	2024-11-18 12:40:24 +01:00
Florent Kermarrec	52148c7aad	soc/integration/soc_core: Fix with_uartbone changes.	2024-11-18 11:07:51 +01:00
Gwenhael Goavec-Merou	211ce59df4	build/lattice/common.py: added Tristate support for ECP5 when build with diamond	2024-11-17 11:32:33 +01:00
enjoy-digital	8041969e00	Merge pull request #2100 from VOGL-electronic/efinix_io_optimize ... efinix: gpio: use constant output option	2024-11-15 09:38:50 +01:00