0545d49294
liteeth/core: add with_icmp parameter
2015-07-06 21:31:20 +02:00
e011f9378f
use sets for leave_out
2015-07-05 22:49:23 +02:00
c100ef6406
liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy)
2015-07-05 22:45:53 +02:00
c1ca928ec2
liteeth: small logic optimizations on mac (eases timings on spartan6)
2015-07-05 12:31:52 +02:00
125432b5b6
liteeth/example_designs: use new Keep SynthesisDirective
2015-06-23 16:15:28 +02:00
01c5051866
liteeth/software: fix wishbone bridge
2015-06-23 01:48:45 +02:00
369cf4c4d7
liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection
2015-06-23 01:08:49 +02:00
5c939b85ef
liteeth/core/arp: fix table timer (wait_timer adaptation issue)
2015-06-23 00:25:26 +02:00
a3c0e5c4d9
liteeth/core/arp: fix missing MAC address in ARP reply
2015-06-22 23:15:00 +02:00
d9b15e6ef6
cores: replace Timeout with new WaitTimer
2015-05-12 16:14:38 +02:00
a99aa9c7fd
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
145398d874
liteeth/core/mac: minor cleanup
2015-05-02 16:48:57 +02:00
63b8797978
liteeth: move mac to core
2015-05-02 16:22:35 +02:00
a4617014f4
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)
2015-05-02 16:22:33 +02:00
3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
c03c41eb77
litescope: rename host directory to software (to be coherent with others cores)
2015-05-01 20:45:02 +02:00
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
d253adee61
liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend
2015-04-28 18:51:40 +02:00
91c77d464c
liteeth: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:06:37 +02:00
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
07b7c2a13f
liteeth/phy/gmii: add default value for pads_register
2015-04-26 14:54:54 +02:00
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
130fd19dec
liteeth/core/ip: simplify ip rx checksum control
2015-04-24 11:31:10 +02:00
5b48e7bb52
liteeth: finish with_preamble_crc vs with_hw_preamble_crc renaming
2015-04-24 11:30:35 +02:00
2d56d32009
liteeth/mac/core: simplify and fix padding
2015-04-24 09:36:33 +02:00
5a930fe7cf
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00
2bd38f44a3
liteeth: more pep8 (when convenient), should be almost OK
2015-04-13 13:02:04 +02:00
154d3d3b04
liteeth: pep8 (E265)
2015-04-13 11:27:01 +02:00
45dc4920ec
liteeth: pep8 (E261, E271)
2015-04-13 11:07:50 +02:00
021a5ae8a0
liteeth: pep8 (W292)
2015-04-13 10:58:45 +02:00
a84f12618b
liteeth: pep8 (E225)
2015-04-13 10:56:18 +02:00
66ce40d880
liteeth: pep8 (E222)
2015-04-13 10:48:59 +02:00
ff2d7f9adc
liteeth: pep8 (E401)
2015-04-13 10:45:09 +02:00
726fd3ab42
liteeth: pep8 (E203)
2015-04-13 10:39:46 +02:00
8dc817dd70
liteeth: pep8 (E231)
2015-04-13 10:31:18 +02:00
9c527742cb
liteeth: pep8 (E201)
2015-04-13 10:23:33 +02:00
5720638d85
liteeth: pep8 (E302)
2015-04-13 10:20:02 +02:00
cd43eaffc2
liteeth: pep8 (replace tabs with spaces)
2015-04-13 09:53:43 +02:00
afa9b889ae
liteeth/phy/gmii: fix clock generation for mii mode (clock_pads.tx is an input)
2015-04-12 22:15:45 +02:00
8e639160e3
liteeth/phy/gmii_mii: add pads registers in RX
2015-04-12 20:43:01 +02:00
0c27708b0a
liteeth/phy/gmii_mii: avoid doubling pads register on TX
2015-04-12 20:42:12 +02:00
bc81d9d639
liteeth/phy/__init__.py: add more comments
2015-04-12 18:56:46 +02:00
515398634f
liteeth/phy/gmii_mii: add clock counter and use it in bios to select mode
2015-04-12 18:42:52 +02:00
857bee8a00
liteeth/phy: add GMII/MII phy
...
for now swicth is manual, we will need a clk counter to allow software or logic to automatically switch between GMII and MII
2015-04-12 17:25:55 +02:00
cfac3d9f5c
liteeth/phy/mii: simplify LiteEthPHYMIIRX using Converter
2015-04-12 16:03:21 +02:00
ddae41f2e4
liteeth/phy/mii: simplify LiteEthPHYMIITX using Converter
2015-04-12 15:34:56 +02:00
8c722db54e
liteeth/phy/mii: assign tx_er only if exists (as it's done on GMII)
2015-04-12 14:43:35 +02:00
4329e3e1b9
liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705)
2015-04-12 14:28:17 +02:00
603a4ef51e
liteeth: adapt to new ModuleTransformer
2015-04-10 11:42:25 +08:00
Florent Kermarrec
Sebastien Bourdeauducq