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Author SHA1 Message Date
Robert Jordens
8798ee8d73 decorators: fix stacklevel, export in std 2015-04-05 18:47:45 +08:00
Robert Jordens
f26ad97624 decorators: fix ControlInserter 2015-04-05 14:44:03 +08:00
Sebastien Bourdeauducq
db76defa2a fhdl/visit: remove TransformModule 2015-04-04 20:12:22 +08:00
Robert Jordens
e702fb7727 decorators: fix class/instance logic 2015-04-04 19:16:58 +08:00
Robert Jordens
4091af69fd fhdl/decorators: make the transform logic more idiomatic 
* the transformers work on classes and instances.
  you can now do just do:

    @ResetInserter()
    @ClockDomainRenamer({"sys": "new"})
    class Foo(Module):
        pass

  or:

    a = ResetInserter()(FooModule())

* the old usage semantics still work
* the old DecorateModule is deprecated,
  ModuleDecorator has been refactored into ModuleTransformer
  (because it not only decorates things)
 2015-04-04 19:16:50 +08:00
Robert Jordens
aac953dd90 vivado: support phys_opt 2015-04-04 19:00:22 +08:00
Robert Jordens
9506f69390 vivado: add support for pre_synthesis_commands 2015-04-04 19:00:01 +08:00
Robert Jordens
4522956f11 vivado: make _build_files() a method and rename 2015-04-04 18:59:50 +08:00
Sebastien Bourdeauducq
1d1189506a mibuild: support multiple specifications of include file and sources 2015-04-04 18:58:02 +08:00
Sebastien Bourdeauducq
357c807eb1 Merge branch 'master' of github.com:m-labs/migen 2015-04-02 20:23:12 +08:00
Yann Sionneau
ce429841d5 kc705: fix typo in platform file (LPC definition) 2015-04-02 20:21:20 +08:00
Florent Kermarrec
ce0ff1e341 remove use of _r prefix on CSRs 2015-04-02 12:15:56 +02:00
Florent Kermarrec
d67f24ddc7 migen/bank/description: remove support of _r prefix in CSRs 2015-04-02 12:13:22 +02:00
Florent Kermarrec
e5ddd1263c remove redundant xilinx_strace_tailor.sh 2015-03-30 18:58:34 +02:00
Sebastien Bourdeauducq
b469571afe move xilinx_strace_tailor to tools 2015-03-30 19:42:11 +08:00
Sebastien Bourdeauducq
c169f0b189 Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions" 
This reverts commit f03aa76292.
 2015-03-30 19:41:16 +08:00
Sebastien Bourdeauducq
dc88295338 Revert "migen/fhdl: pass fdict filename --> contents to specials" 
This reverts commit ea04947519.
 2015-03-30 19:41:13 +08:00
Sebastien Bourdeauducq
b1c811a3d1 Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method" 
This reverts commit 95cfc444e6.
 2015-03-30 19:41:04 +08:00
Florent Kermarrec
15e24b6c10 mibuild/platforms: fix minispartan6 2015-03-30 11:42:14 +02:00
Florent Kermarrec
95cfc444e6 migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method 2015-03-30 11:37:59 +02:00
Florent Kermarrec
ea04947519 migen/fhdl: pass fdict filename --> contents to specials 2015-03-30 11:37:57 +02:00
Florent Kermarrec
f03aa76292 migen: create VerilogConvert and EDIFConvert classes and return it with convert functions 2015-03-30 11:37:55 +02:00
Sebastien Bourdeauducq
21c5fb6f6c Merge branch 'master' of github.com:m-labs/migen 2015-03-30 00:52:15 +08:00
Sebastien Bourdeauducq
19a6157478 platforms/lx9_microboard,usrp_b100: fix bitgen opts 2015-03-30 00:44:56 +08:00
Florent Kermarrec
263fc47728 platforms/kc705: fix .bin generation with ISE and Vivado 2015-03-29 21:15:20 +08:00
Florent Kermarrec
17f3590a7c platforms/kc705: add iMPACT programmer 2015-03-29 12:15:39 +02:00
Sebastien Bourdeauducq
72fae61525 Merge branch 'master' of https://github.com/m-labs/migen 2015-03-27 19:22:03 +01:00
Robert Jordens
20b646bd1a add tool to build minimal xilinx toolchains 2015-03-27 19:21:47 +01:00
Florent Kermarrec
ec080479da mibuild/sim: use the same architecture we use for others backends 2015-03-27 14:14:49 +01:00
Florent Kermarrec
de31103cce platforms/minispartan6: add ftdi_fifo pins 2015-03-22 11:20:22 +01:00
Florent Kermarrec
200979fb81 platforms/minispartan6: fix IOStandard/Slew, add FpgaProg programmer, change default clock to 32MHz 2015-03-22 03:37:27 +01:00
Florent Kermarrec
7440ccd65b mibuild/xilinx/programmer: add iMPACT programmer (for sb: I need it in Windows for now since I was not able to get XC3SPROG working) 2015-03-21 20:27:11 +01:00
Florent Kermarrec
1d2e7e8390 mibuild/platforms/minispartan6: adapt to recent changes (able to build simple example) 2015-03-21 18:31:50 +01:00
Florent Kermarrec
78b4f313bf mibuild/platforms/minispartan6: add device parameter (board can be populated with lx9 or lx25) 2015-03-21 18:28:09 +01:00
Florent Kermarrec
1a03c340c9 mibuild/platforms: review and fix small mistakes 2015-03-21 18:23:35 +01:00
Florent Kermarrec
3a38626556 mibuild/platforms: add minispartan6 (from Matt O'Gorman) 2015-03-21 18:22:26 +01:00
Robert Jordens
14b1da4018 test_actor: add unittests for SimActor 
* also implicitly tests for the access of signals during simulation that are
not referenced in any statements

* before, if the busy signal is never used, it is stripped
  and could not be accessed in simulation
 2015-03-21 10:02:10 +01:00
Robert Jordens
5f045b7649 sim: keep track of unreferenced items 
* items that are never referenced in any statements do not end up in the
namespace or in the verilog

* this memorizes items if they can not be found in the namespace and keeps
track of their values
 2015-03-21 10:02:10 +01:00
Robert Jordens
4fe888702d pipistrello: switch is a button 2015-03-19 18:56:49 +01:00
Robert Jordens
47ea451315 pipistrello: compress and load bitstream at 6MHz 2015-03-19 18:48:45 +01:00
Robert Jordens
860b72c8b6 pipistrello: rename sdram->ddram 2015-03-19 18:48:22 +01:00
Sebastien Bourdeauducq
7fa1cd72a8 fhdl/verilog: fix dummy signal initial event 2015-03-19 00:24:30 +01:00
Florent Kermarrec
3aee58f484 mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented) 2015-03-18 18:54:22 +01:00
Florent Kermarrec
5a9afee234 fhdl/specials/memory: use $readmemh to initialize memories 2015-03-18 15:27:01 +01:00
Florent Kermarrec
c0fb0ef600 fhdl/verilog: change the way we initialize reg: reg name = init_value; 
This allows simplifications (init in _printsync and _printinit no longer needed)
 2015-03-18 15:05:26 +01:00
Florent Kermarrec
ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code" 
This probably breaks simulation with Icarus Verilog (and others simulators?)
 2015-03-18 14:59:22 +01:00
Florent Kermarrec
2fc2f8a6c0 migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb) 2015-03-18 14:41:43 +01:00
Sebastien Bourdeauducq
bdc47b205a Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)" 
This breaks simulations, and we will try to use the "reg name = value" syntax instead.

This reverts commit e946f6e453.
 2015-03-18 12:08:25 +01:00
Florent Kermarrec
89fefef3f8 genlib/io: add optional external rst to CRG 2015-03-17 16:22:22 +01:00
Florent Kermarrec
500e58ce7d mibuild/platform/versa: fix clock_constraints 2015-03-17 15:25:10 +01:00