Nina Engelhardt
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4ebbfa63bf
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add mist synthesis mode to build
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2013-08-12 13:13:25 +02:00 |
Sebastien Bourdeauducq
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88611be368
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xilinx_ise: cleanup
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2013-08-08 00:15:35 +02:00 |
user
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9d531ba06a
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Fix missing string replace. Added support for 32-bit ISE if 64-bit version is missing on 64-bit system.
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2013-08-08 00:07:35 +02:00 |
Nina Engelhardt
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6e64016885
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add edif build routines
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2013-08-03 10:55:12 +02:00 |
|
Sebastien Bourdeauducq
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b18cffb5e8
|
xilinx_ise: run tools like Project Navigator does to avoid weird bitgen behavior
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2013-07-04 23:49:12 +02:00 |
|
Sebastien Bourdeauducq
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05bc2885e9
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Call finalize() after CRG creation
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2013-07-04 19:49:39 +02:00 |
|
Sebastien Bourdeauducq
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0883e99de3
|
Do not specify period constraints twice
|
2013-07-04 19:25:29 +02:00 |
Robert Jordens
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e233c62d27
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* generic_platform.py: add a finalize() method
... to add e.g. timing constraints after the other modules have
had their say and when the signal names are known
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2013-06-27 19:17:02 +02:00 |
|
Sebastien Bourdeauducq
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953e603915
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xilinx_ise: improve parameter passing
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2013-06-01 17:22:57 +02:00 |
|
Sebastien Bourdeauducq
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759858f739
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Use migen.fhdl.std
|
2013-05-26 18:07:26 +02:00 |
|
Sebastien Bourdeauducq
|
439f032921
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crg: support for resetless system clock domain
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2013-05-07 19:09:56 +02:00 |
|
Sebastien Bourdeauducq
|
e4b0e8ed6d
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xilinx_ise: enable register balancing
|
2013-05-06 14:21:39 +02:00 |
|
Sebastien Bourdeauducq
|
85e06cc100
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xilinx_ise: implement NoRetiming synthesis constraint
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2013-04-25 14:57:45 +02:00 |
|
Sebastien Bourdeauducq
|
29eaf068f3
|
xilinx_ise: do not attempt to source settings file on Windows
|
2013-04-16 22:55:24 +02:00 |
|
Sebastien Bourdeauducq
|
31b1960188
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xilinx_ise: add --no-source option to disable sourcing of ISE settings file
|
2013-04-16 22:39:35 +02:00 |
|
Sebastien Bourdeauducq
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715d332c3d
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crg: apply constraint to IO pins, not internal signals
|
2013-04-08 20:28:11 +02:00 |
|
Sebastien Bourdeauducq
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8cf7c96a53
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crg: use new platform.request
|
2013-03-26 23:08:35 +01:00 |
|
Sebastien Bourdeauducq
|
3b19dfc412
|
Support for platform info
|
2013-03-26 19:17:35 +01:00 |
|
Sebastien Bourdeauducq
|
003f1950cd
|
xilinx_ise: fix clock domain names
|
2013-03-23 19:37:16 +01:00 |
|
Sebastien Bourdeauducq
|
4bf3190244
|
MultiReg: remove idomain
|
2013-03-15 19:54:25 +01:00 |
|
Sebastien Bourdeauducq
|
6feb6e60b0
|
New clock_domain API
|
2013-03-15 18:46:11 +01:00 |
|
Sebastien Bourdeauducq
|
71c8172836
|
xilinx_ise/CRG_SE: reset inversion support
|
2013-03-15 11:31:36 +01:00 |
|
Sebastien Bourdeauducq
|
6a412f796e
|
xilinx_ise: add lock cycle to bitgen
|
2013-03-01 11:29:40 +01:00 |
|
Sebastien Bourdeauducq
|
2b902fdcbd
|
xilinx_ise: import Instance
|
2013-02-24 15:36:56 +01:00 |
|
Sebastien Bourdeauducq
|
d60ab1d215
|
Use new 'specials' API
|
2013-02-24 12:21:01 +01:00 |
|
Sebastien Bourdeauducq
|
56ae0f0714
|
xilinx_ise: disable SRL extraction on synchronizers
|
2013-02-23 19:43:12 +01:00 |
|
Sebastien Bourdeauducq
|
f13ad035e1
|
Support for command line arguments
|
2013-02-08 22:23:58 +01:00 |
|
Sebastien Bourdeauducq
|
b092237fa6
|
xilinx_ise: support building files without running ISE
|
2013-02-08 20:31:45 +01:00 |
|
Sebastien Bourdeauducq
|
7b8e8a19f3
|
Support adding Verilog/VHDL files
|
2013-02-08 20:25:20 +01:00 |
|
Sebastien Bourdeauducq
|
fb5130fc1f
|
Initial version
|
2013-02-07 22:07:30 +01:00 |