Florent Kermarrec
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ea613cd8ee
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litesata: update build core target generation
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2015-04-09 00:00:25 +02:00 |
|
Florent Kermarrec
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03aa972bb6
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lite*: finish ModuleTransformer adaptations (need to be tested on board)
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2015-04-08 23:27:22 +02:00 |
Robert Jordens
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66f8dcbfaf
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lite*: adapt to new ModuleTransformer semantics
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
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2015-04-04 19:17:24 +08:00 |
|
Florent Kermarrec
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60124be293
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adapt LiteSATA to new SoC
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2015-04-01 22:52:19 +02:00 |
Sebastien Bourdeauducq
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6e2a662dd7
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litesata: adapt to new SoC API
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2015-04-01 17:37:53 +08:00 |
|
Florent Kermarrec
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9107710f03
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litexxx cores: use default baudrate of 115200 for all tests
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2015-03-20 12:22:53 +01:00 |
|
Florent Kermarrec
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236ea0f572
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liteeth: use bios ip_address in example designs
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2015-03-18 18:18:43 +01:00 |
|
Florent Kermarrec
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a266deb58e
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LiteXXX cores: fix frequency print in test/test_regs.py
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2015-03-17 16:01:25 +01:00 |
|
Florent Kermarrec
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d2cb41bc63
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LiteXXX cores: convert port parameter to int if is digit in test/make.py
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2015-03-17 15:58:21 +01:00 |
|
Florent Kermarrec
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d8b59c03a2
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litesata: avoid hack on kc705 platform with new mibuild toolchain management
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2015-03-14 01:08:36 +01:00 |
|
Florent Kermarrec
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52f1c45407
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LiteXXX cores: fix test_reg.py
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2015-03-04 23:13:14 +01:00 |
|
Sebastien Bourdeauducq
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073641faa1
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litesata: fix permissions and imports
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2015-03-04 00:46:24 +00:00 |
|
Florent Kermarrec
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1d4dc45436
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LiteXXX cores: use format in prints
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2015-03-03 10:29:28 +01:00 |
|
Florent Kermarrec
|
f27e7a4b22
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litesata: remove unneeded clock constraint
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2015-03-03 10:24:05 +01:00 |
|
Sebastien Bourdeauducq
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ff29c86fe1
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litesata/kc705: use FMC pin names
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2015-03-03 01:02:50 +00:00 |
|
Florent Kermarrec
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649cdeb265
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liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
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2015-03-01 16:48:41 +01:00 |
|
Florent Kermarrec
|
9e01bf5fdd
|
litesata: create example design derived from SoC
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2015-03-01 11:33:38 +01:00 |
|
Florent Kermarrec
|
c21a7956c8
|
liteXXX cores: remove Identifier duplication
|
2015-03-01 11:24:58 +01:00 |
|
Florent Kermarrec
|
67ca0da1d9
|
liteXXX cores: share same methodology for on-board tests
|
2015-03-01 11:21:12 +01:00 |
|
Florent Kermarrec
|
7b464b2b1c
|
litesata: create specialized kc705 platform to avoid duplicating things already in mibuild
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2015-03-01 11:03:15 +01:00 |
|
Florent Kermarrec
|
b34be816ec
|
liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
|
2015-02-28 22:23:48 +01:00 |
|
Florent Kermarrec
|
0fd1b9df8d
|
liteXXX cores: remove redefinition of get_csr_csv
|
2015-02-28 21:45:05 +01:00 |
|
Florent Kermarrec
|
5bd1ab7fa1
|
liteXXX cores: update README and doc
|
2015-02-28 21:40:59 +01:00 |
|
Florent Kermarrec
|
69e869893d
|
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |
|
Florent Kermarrec
|
8e67d6e69f
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liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
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2015-02-28 11:08:17 +01:00 |
|
Florent Kermarrec
|
0dfca49e68
|
litesata: move file and modify import to misoclib.mem.litesata
|
2015-02-28 11:03:24 +01:00 |
|
Florent Kermarrec
|
b6358be0a1
|
merge litesata
|
2015-02-28 10:48:08 +01:00 |