Sebastien Bourdeauducq
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ecfe1646ec
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fhdl/verilog: implicit get_fragment
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2013-03-12 16:16:06 +01:00 |
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Sebastien Bourdeauducq
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c06a821452
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generic_platform: implicit get_fragment
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2013-03-12 16:14:13 +01:00 |
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Sebastien Bourdeauducq
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1e7783a41e
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build.py: use implicit get_fragment
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2013-03-12 16:13:20 +01:00 |
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Sebastien Bourdeauducq
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4ada2ead05
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fhdl/specials/Memory: automatic name#
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2013-03-12 15:58:39 +01:00 |
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Sebastien Bourdeauducq
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a23df42a7a
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Use automatic register naming
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2013-03-12 15:47:54 +01:00 |
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Sebastien Bourdeauducq
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04df076fba
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bank: automatic register naming
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2013-03-12 15:45:24 +01:00 |
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Sebastien Bourdeauducq
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7e2581bf17
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fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
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2013-03-12 13:48:09 +01:00 |
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Sebastien Bourdeauducq
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12158ceadf
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fhdl/tracer: recognize LOAD_DEREF opcode
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2013-03-12 10:31:56 +01:00 |
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Sebastien Bourdeauducq
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3c75121783
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fhdl/tracer: remove leading underscores from names
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2013-03-11 22:21:58 +01:00 |
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Sebastien Bourdeauducq
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c4d9734e53
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README: update
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2013-03-11 20:29:47 +01:00 |
Florent Kermarrec
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60e2cdfe79
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get_registers --> get_registers_glue since it's conflicting with new Migen register automatic detection
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2013-03-11 20:05:30 +01:00 |
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Sebastien Bourdeauducq
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80970b203c
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bus/asmibus: use implicit finalization
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2013-03-11 17:11:59 +01:00 |
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Sebastien Bourdeauducq
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b042757187
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Fix Register name conflict between Pytholite and Bank
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2013-03-10 19:47:21 +01:00 |
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Sebastien Bourdeauducq
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a9b723568a
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Use new module, autoreg and eventmanager Migen APIs
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2013-03-10 19:32:38 +01:00 |
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Sebastien Bourdeauducq
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f93695f60e
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bank/eventmanager: use module and autoreg
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2013-03-10 19:29:05 +01:00 |
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Sebastien Bourdeauducq
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174e8cb8d6
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bus/asmibus: use fhdl.module API
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2013-03-10 19:28:22 +01:00 |
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Sebastien Bourdeauducq
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17e0dfe120
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fhdl/module: replace autofragment
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2013-03-10 19:27:55 +01:00 |
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Sebastien Bourdeauducq
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cddbc1157d
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bank/description/AutoReg: check that get_memories and get_registers are callable
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2013-03-10 18:11:29 +01:00 |
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Sebastien Bourdeauducq
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68fe4c269c
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bank/csrgen: BankArray
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2013-03-10 00:45:16 +01:00 |
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Sebastien Bourdeauducq
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f1474420df
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bank/description: AutoReg
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2013-03-10 00:43:16 +01:00 |
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Sebastien Bourdeauducq
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d0676e2dd1
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migen/fhdl/autofragment: factorize
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2013-03-09 23:23:24 +01:00 |
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Sebastien Bourdeauducq
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d0d2df3c4b
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fhdl/autofragment: remove legacy functions
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2013-03-09 23:05:45 +01:00 |
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Sebastien Bourdeauducq
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72fb6fd6bd
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fhdl/tools/flat_iteration: generalize
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2013-03-09 23:03:15 +01:00 |
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Sebastien Bourdeauducq
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f53acb92e7
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fhdl/autofragment: fix submodules
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2013-03-09 21:15:38 +01:00 |
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Sebastien Bourdeauducq
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6da8eb906f
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fhdl/autofragment: empty build_fragment by default
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2013-03-09 19:10:47 +01:00 |
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Sebastien Bourdeauducq
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2b8dc52c13
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Use common definition for FinalizeError
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2013-03-09 19:03:13 +01:00 |
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Sebastien Bourdeauducq
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b75fb7f97c
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csr/SRAM: support for writes with memory widths larger than bus words
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2013-03-09 00:50:57 +01:00 |
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Sebastien Bourdeauducq
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6fa30053bf
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fhdl/verilog: tristate outputs are always wire
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2013-03-06 11:30:52 +01:00 |
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Sebastien Bourdeauducq
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2059592db2
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software/libcompiler-rt: add ctzsi2
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2013-03-06 11:10:16 +01:00 |
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Sebastien Bourdeauducq
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4d4d6c1f88
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platforms/m1: add video mixer extension board
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2013-03-05 23:03:01 +01:00 |
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Sebastien Bourdeauducq
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9b4ca987e0
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bus/csr: support memories with larger word width than the bus (read only)
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2013-03-03 19:27:13 +01:00 |
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Sebastien Bourdeauducq
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bb5ee8d3bd
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fhdl/autofragment: bugfixes + add auto_attr
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2013-03-03 17:53:06 +01:00 |
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Sebastien Bourdeauducq
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cc8118d35c
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fhdl/autofragment: FModule
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2013-03-02 23:30:54 +01:00 |
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Sebastien Bourdeauducq
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d2491828a4
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csr/SRAM: prefix page register with memory name
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2013-03-01 12:06:12 +01:00 |
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Sebastien Bourdeauducq
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6a412f796e
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xilinx_ise: add lock cycle to bitgen
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2013-03-01 11:29:40 +01:00 |
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Florent Kermarrec
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edce543b14
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adapt to migen changes
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2013-03-01 01:09:00 +01:00 |
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Florent Kermarrec
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80e9db7e61
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use mibuild for de1 example
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2013-02-28 23:11:41 +01:00 |
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Florent Kermarrec
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58a6acba27
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use mibuild for de0_nano example
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2013-02-28 23:02:06 +01:00 |
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Florent Kermarrec
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58edd7632c
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compiles but untested
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2013-02-28 00:32:42 +01:00 |
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Sebastien Bourdeauducq
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c10622f5e2
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fhdl/verilog: insert reset before listing signals
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2013-02-27 18:10:04 +01:00 |
|
Florent Kermarrec
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5accd48a17
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doc: update
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2013-02-26 23:45:01 +01:00 |
|
Florent Kermarrec
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87336128a3
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sim: update
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2013-02-26 23:25:10 +01:00 |
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Florent Kermarrec
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ae900c9c16
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examples: use miscope.bridges
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2013-02-26 23:20:29 +01:00 |
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Florent Kermarrec
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5fc89f0c71
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move spi2csr to briges/spi2csr
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2013-02-26 23:17:34 +01:00 |
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Florent Kermarrec
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f823d06cf1
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examples: update & simplify
|
2013-02-26 23:14:09 +01:00 |
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Florent Kermarrec
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b3ae31ee2f
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examples/../top: update
|
2013-02-26 23:00:37 +01:00 |
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Sebastien Bourdeauducq
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d2cbc70190
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bank/description: memprefix
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2013-02-25 23:14:15 +01:00 |
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Sebastien Bourdeauducq
|
a81781f589
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fhdl/specials: allow setting memory name
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2013-02-25 23:14:03 +01:00 |
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Sebastien Bourdeauducq
|
425de02f42
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uio/ioo: fix specials
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2013-02-25 23:13:38 +01:00 |
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Sebastien Bourdeauducq
|
356416fcdc
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lm32: update
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2013-02-24 17:42:28 +01:00 |