Sebastien Bourdeauducq
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0392dd8ac2
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bank/csrgen: interface -> bus
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2012-12-06 17:15:47 +01:00 |
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Sebastien Bourdeauducq
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e89c66bf14
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bank/csrgen: interface -> bus
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2012-12-06 17:15:34 +01:00 |
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Sebastien Bourdeauducq
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273d9d285b
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bank/description: define reset value of read signal
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2012-12-05 16:40:44 +01:00 |
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Sebastien Bourdeauducq
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34ce934809
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actorlib/sim: drive busy high until generator is finished
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2012-12-05 16:40:12 +01:00 |
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Sebastien Bourdeauducq
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4bcb39699b
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bus/wishbone/sram: accept memories < 32 bits
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2012-12-01 13:04:22 +01:00 |
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Sebastien Bourdeauducq
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bec02c4783
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Merge branch 'master' of github.com:milkymist/milkymist-ng
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2012-12-01 12:59:47 +01:00 |
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Sebastien Bourdeauducq
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fee70e9866
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Use Wishbone SRAM component from Migen
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2012-12-01 12:59:32 +01:00 |
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Sebastien Bourdeauducq
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523816982a
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bus/wishbone: add SRAM
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2012-12-01 12:59:09 +01:00 |
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Sebastien Bourdeauducq
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adb1565d7a
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pytholite: fix bit width of selection signal
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2012-11-30 17:07:32 +01:00 |
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Sebastien Bourdeauducq
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cfb23c442f
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pytholite: support signed registers
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2012-11-30 17:07:12 +01:00 |
Michael Walle
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7a1e4cb66b
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lm32: fix watchpoints
The wp_match_n vector is off by one. Which results in undefined states, at
least in simulation.
Signed-off-by: Michael Walle <michael@walle.cc>
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2012-11-30 15:22:40 +01:00 |
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Sebastien Bourdeauducq
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7093939309
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corelogic/roundrobin: fix request width (again)
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2012-11-29 23:47:51 +01:00 |
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Sebastien Bourdeauducq
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31c722f993
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corelogic/roundrobin: fix request width
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2012-11-29 23:47:08 +01:00 |
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Sebastien Bourdeauducq
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293a62dabe
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Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 23:41:51 +01:00 |
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Sebastien Bourdeauducq
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8bf6945dfd
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Use new bitwidth/signedness system
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2012-11-29 23:38:04 +01:00 |
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Sebastien Bourdeauducq
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70e97e0456
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Fix various errors from new bitwidth/signedness system conversion
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2012-11-29 23:36:55 +01:00 |
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Sebastien Bourdeauducq
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261166d92b
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fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
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2012-11-29 22:59:54 +01:00 |
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Sebastien Bourdeauducq
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55d143a454
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fhdl/structure: add unary minus
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2012-11-29 22:52:57 +01:00 |
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Sebastien Bourdeauducq
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d8e478efee
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Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 21:53:36 +01:00 |
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Sebastien Bourdeauducq
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50ed73c937
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New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
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Sebastien Bourdeauducq
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6eebfce44a
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Refactor Case
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2012-11-29 01:11:15 +01:00 |
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Sebastien Bourdeauducq
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070652cc39
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pytholite/reg: use source id in dictionary
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2012-11-29 00:09:35 +01:00 |
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Sebastien Bourdeauducq
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7e2bc00c0a
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Remove Constant
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2012-11-28 23:18:53 +01:00 |
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Sebastien Bourdeauducq
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fee22a4631
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Remove Constant
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2012-11-28 23:18:43 +01:00 |
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Sebastien Bourdeauducq
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79e5f24a65
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Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.
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2012-11-28 22:49:22 +01:00 |
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Sebastien Bourdeauducq
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2a3ef28041
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examples/sim/dataflow: update to new APIs
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2012-11-28 22:44:14 +01:00 |
|
Sebastien Bourdeauducq
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39d577d65e
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examples/dataflow/dma: update to new APIs
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2012-11-28 22:42:01 +01:00 |
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Sebastien Bourdeauducq
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7c4b5931bc
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examples/basic: remove unroll example
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2012-11-28 22:16:02 +01:00 |
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Sebastien Bourdeauducq
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59831e0485
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fhdl/structure: improved bits_for function
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2012-11-28 18:39:44 +01:00 |
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Sebastien Bourdeauducq
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11b1e53224
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visit/NodeTransformer: copy most nodes
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2012-11-28 17:50:55 +01:00 |
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Sebastien Bourdeauducq
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a2bcbfdf8f
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fhdl/tools: use NodeTransformer to lower arrays
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2012-11-28 17:46:15 +01:00 |
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Sebastien Bourdeauducq
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5440fa715c
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examples/basic/arrays: add array assignment to fragment
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2012-11-26 22:47:35 +01:00 |
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Sebastien Bourdeauducq
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3bc15024ac
|
fhdl/tools: use NodeVisitor
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2012-11-26 21:40:23 +01:00 |
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Sebastien Bourdeauducq
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e3a983d731
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Remove unroll
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2012-11-26 20:07:48 +01:00 |
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Sebastien Bourdeauducq
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1460f069f6
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fhdl/structure: remove deprecated MemoryPort
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2012-11-26 19:36:43 +01:00 |
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Sebastien Bourdeauducq
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0620e75cb8
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sram: do not use MemoryPort
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2012-11-26 19:32:56 +01:00 |
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Sebastien Bourdeauducq
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5183774ec8
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bus/wishbone2asmi: do not use MemoryPort
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2012-11-26 19:14:59 +01:00 |
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Sebastien Bourdeauducq
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fc85ca53ad
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actorlib/spi: do not use MemoryPort
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2012-11-26 18:27:59 +01:00 |
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Sebastien Bourdeauducq
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0c29775a8f
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tb/asmicon/asmicon_wb: more complete testing by default
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2012-11-26 18:19:41 +01:00 |
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Sebastien Bourdeauducq
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2418367c7a
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examples/sim/memory: do not use MemoryPort
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2012-11-26 18:19:10 +01:00 |
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Sebastien Bourdeauducq
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dac0d11e52
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actorlib/sim: Dumper
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2012-11-24 00:00:07 +01:00 |
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Sebastien Bourdeauducq
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27d87c9412
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fhdl/structure: disable we_granularity when larger than width
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2012-11-23 23:08:12 +01:00 |
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Sebastien Bourdeauducq
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d2c61e6a90
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sim/generic/multiread: do not return spurious items
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2012-11-23 23:07:25 +01:00 |
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Sebastien Bourdeauducq
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74721b206f
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pytholite: fix import of _Slice
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2012-11-23 21:20:18 +01:00 |
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Sebastien Bourdeauducq
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95122bb778
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pytholite/io: support memory
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2012-11-23 20:36:09 +01:00 |
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Sebastien Bourdeauducq
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f42683b71e
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fhdl/structure/Memory: fix we width
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2012-11-23 19:21:52 +01:00 |
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Sebastien Bourdeauducq
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784a399431
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examples/memory: use new get_port API
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2012-11-23 19:18:08 +01:00 |
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Sebastien Bourdeauducq
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0f6215a13a
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fhdl/structure: add Memory.get_port API
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2012-11-23 19:17:49 +01:00 |
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Sebastien Bourdeauducq
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9d3e218863
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fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
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2012-11-23 18:38:03 +01:00 |
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Sebastien Bourdeauducq
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3971600917
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fhdl/structure: use sets for memories and instance collections
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2012-11-23 17:20:08 +01:00 |