28b0c340af
corelogic/record: add to_signal convenience function
2012-02-11 20:55:23 +01:00
e62ac1d3a1
corelogic/misc: contiguous split
2012-02-11 11:52:15 +01:00
ef436a1ec9
bus/asmibus: add get_slots, fix get_fragment
2012-02-10 17:49:06 +01:00
945d655d45
bus: ASMI hub (untested)
2012-02-10 15:21:04 +01:00
c1bff38861
doc: update Bank description
2012-02-08 19:26:56 +01:00
0654bf4583
tools: use install and /usr/local (as suggested by David Kuehling)
2012-02-08 15:09:07 +01:00
bfd2bf4ed3
tools: remove bin2hex
2012-02-08 15:08:03 +01:00
755079d7fa
libbase: blocking UART write if IRQs are enabled
2012-02-07 15:12:27 +01:00
73fce59631
software: shell from original BIOS
2012-02-07 15:02:44 +01:00
ef0667d959
software: UART RX demo
2012-02-07 14:12:33 +01:00
506ffab11a
uart: RX support
2012-02-07 14:12:23 +01:00
fb22edc06a
software: enable -Wmissing-prototypes
2012-02-07 13:02:06 +01:00
63f6dece56
software: use the Clang/LLVM compiler
2012-02-07 12:52:34 +01:00
a40b0ea175
software: fix size_t and ptrdiff_t
2012-02-07 12:06:49 +01:00
494c383fa8
software: remove unnecessary IRQ acks
2012-02-07 00:07:25 +01:00
b6b1901bb8
LM32: make IP read-only and interrupt lines level-sensitive
2012-02-07 00:07:12 +01:00
4aaf48afb0
software: interrupt driven UART working
2012-02-06 23:53:29 +01:00
58f4f78d2c
sram: fix sub-word write
2012-02-06 23:13:35 +01:00
47883675db
bus/wishbone2csr: truncate WB data
2012-02-06 18:43:34 +01:00
1eb348c573
fhdl: do not attempt slicing non-array signals to keep Verilog happy
2012-02-06 18:07:02 +01:00
5cde57cb65
software: use new UART
2012-02-06 17:53:41 +01:00
33f1c456bf
top: connect UART IRQ
2012-02-06 17:45:40 +01:00
5dc875de69
UART: use new bank API and event manager
2012-02-06 17:45:31 +01:00
fcd6583cbb
bank: event manager
2012-02-06 17:39:32 +01:00
3a2a0c4dd8
bank: support registers larger than the bus word width
2012-02-06 16:15:27 +01:00
f3ddfffc47
bank: refactoring
2012-02-06 13:55:50 +01:00
1a86f26a66
bank/csrgen: use enumerate
2012-02-06 11:18:30 +01:00
45529d5941
BIOS: hello world
2012-02-05 20:01:28 +01:00
33da32417a
Update gitignore
2012-02-05 20:01:14 +01:00
9b9a510525
Memory map
2012-02-05 19:54:08 +01:00
629e771fc0
fhdl/structure: binary constant builder
2012-02-05 19:32:11 +01:00
17cd8dd479
Add tools
2012-02-05 19:14:24 +01:00
e2317bc83b
flash: remove splash screens
2012-02-05 19:12:33 +01:00
1ad44b6571
software: dependencies the Werner way
2012-02-03 12:25:55 +01:00
1a4a6eb445
Copy some software code from the original Milkymist SoC.
...
Libbase should keep its RAM usage to a minimum as it is meant to
be executed before the SDRAM is up and running. (Having lots of
code is OK though as we XIP from the flash)
2012-02-03 12:08:17 +01:00
b5cb1083ab
sram: fix WE signal
2012-02-03 10:38:17 +01:00
504a169afb
Merge pull request #2 from larsclausen/master
...
migen patches
2012-02-03 01:25:38 -08:00
8380318e84
Use enumerate(x) instead of zip(range(x), x)
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2012-02-02 21:28:00 +01:00
2b3f00cbc1
fhdl/namer: Add support for STORE_DEREF opcode
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2012-02-02 21:15:10 +01:00
9f05e7235d
Lower required python version to 3.1
...
migen is confirmed to work fine with python 3.1, so lower the required version
from 3.2 to 3.1.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2012-02-02 21:15:07 +01:00
3143608e0a
examples/wb_intercon: update to new APIs
2012-01-28 23:18:21 +01:00
6a9b59786b
fhdl/namer: extract variable names with bytecode inspection
2012-01-28 23:17:44 +01:00
5c2df45577
fhdl: do not prefix instance signal names
2012-01-28 11:39:28 +01:00
8a2646a549
Remove explicit bus names
2012-01-27 22:21:08 +01:00
a99c2acfa8
Remove explicit bus names and rely on the new automatic namer
2012-01-27 22:20:57 +01:00
28f00c3a9a
Add on-chip SRAM
2012-01-27 22:09:03 +01:00
685b5eb08f
fhdl: support memory read enable
2012-01-27 21:39:23 +01:00
0cc7e2ac1e
fhdl: make WRITE_FIRST default
2012-01-27 21:35:58 +01:00
2726ba2242
doc: memories
2012-01-27 21:23:17 +01:00
5405a83ff9
fhdl: memories working
2012-01-27 20:22:17 +01:00
Sebastien Bourdeauducq
Sébastien Bourdeauducq
Lars-Peter Clausen