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5552 Commits

Author SHA1 Message Date
Florent Kermarrec 5b0a8a798f add test_MigLa.py (Wip) 
fixes
 2012-09-14 14:08:20 +02:00
Florent Kermarrec 79af96c190 add access methods 2012-09-14 12:57:09 +02:00
Florent Kermarrec cde176a0b7 migScope/tools/truthtable.py: add function to remove duplicate operands 2012-09-14 12:26:48 +02:00
Florent Kermarrec aac16a9e11 add test_MigIo.py for de0_nano and de1 example 2012-09-13 13:18:03 +02:00
Florent Kermarrec 619671ad73 fix write function 2012-09-13 13:15:05 +02:00
Florent Kermarrec 8e86be1a6a add address parameter to migIo 2012-09-13 13:14:27 +02:00
Florent Kermarrec f4369c917f add spi2Csr tools : Python Host & Arduino Uart<-->Spi bridge 2012-09-13 11:34:19 +02:00
Florent Kermarrec c7e2b0c43e examples/de1: use of MigIo 2012-09-12 22:20:07 +02:00
Florent Kermarrec fc6225273b add MigIo Class 2012-09-12 22:19:42 +02:00
Florent Kermarrec bb6045e279 update README 2012-09-12 18:09:12 +02:00
Florent Kermarrec af64beec53 examples/de1: fix top 2012-09-12 18:07:36 +02:00
Florent Kermarrec fb624fddc4 initialize de1 example 2012-09-12 17:56:36 +02:00
Florent Kermarrec 24b7ba8722 examples/de0_nano : add load cmd / change rst polarity 2012-09-12 16:53:08 +02:00
Sebastien Bourdeauducq 2e14569b5c fhdl/verilog: sort clock domains by name 2012-09-11 10:00:03 +02:00
Sebastien Bourdeauducq 9a18a9df3f fhdl: list signals in execution order 2012-09-11 09:59:37 +02:00
Sebastien Bourdeauducq c86dd3cbef Define clock domains instead of passing extra clocks as regular signals 2012-09-11 00:21:07 +02:00
Sebastien Bourdeauducq 3b3e2f19eb Merge branch 'master' of github.com:milkymist/migen 2012-09-11 00:09:11 +02:00
Sebastien Bourdeauducq 5931c5eb59 Basic support for new clock domain and instance API 2012-09-10 23:47:06 +02:00
Sebastien Bourdeauducq fc3187317b examples: demonstrate multi-clock support 2012-09-10 23:46:19 +02:00
Sebastien Bourdeauducq f7b1e67d08 examples: update LM32 instance 2012-09-10 23:45:27 +02:00
Sebastien Bourdeauducq e16353a281 Multi-clock design support + new instance API 2012-09-10 23:45:02 +02:00
Florent Kermarrec 4a59b63151 Clean up 2012-09-09 23:46:26 +02:00
Florent Kermarrec 7a24ee7027 Wip de0_nano example 2012-09-09 23:27:51 +02:00
Florent Kermarrec 6b8dda03c6 Wip de0_nano example 2012-09-09 22:32:09 +02:00
Florent Kermarrec 1578c74895 Initialize de0_nano example 2012-09-09 21:18:09 +02:00
Florent Kermarrec b8eaf0906a Clean up 2012-09-09 20:51:15 +02:00
Florent Kermarrec 2092c5a138 add global tb, fix bugs 2012-09-09 20:38:01 +02:00
Sebastien Bourdeauducq f40ca52e5f setup.py: cosmetic 2012-09-09 19:56:04 +02:00
Sébastien Bourdeauducq 6490785b6c Merge pull request #3 from brandonhamilton/upstream 
Optionally accept iverilog simulator options
 2012-09-09 10:52:52 -07:00
Sebastien Bourdeauducq 2a7d2908d1 examples: new namer 2012-09-09 19:34:46 +02:00
Sebastien Bourdeauducq b45c9546eb fhdl/namer: better handling of indices 2012-09-09 19:33:55 +02:00
Sebastien Bourdeauducq 589251fffd fhdl/tracer: support BUILD_LIST opcode 2012-09-09 18:53:24 +02:00
Sebastien Bourdeauducq 910c350021 fhdl/namer: use execution order indices for variable names as well 2012-09-09 17:31:35 +02:00
Florent Kermarrec 289d35b952 simplify registers mgnt 2012-09-09 14:37:55 +02:00
Sebastien Bourdeauducq f3e3a3eec7 fhdl/namer: number objects according to execution order 2012-09-09 12:27:32 +02:00
Sebastien Bourdeauducq 51f9a2a963 fhdl/namer: simplify + more relevant names 2012-09-09 01:26:33 +02:00
Florent Kermarrec 2abd7f664d add tb_RecorderCsr.py 
fixs in recorder.py
 2012-08-27 00:44:26 +02:00
Florent Kermarrec d34c877401 split migScope to trigger & recorder 2012-08-26 21:30:23 +02:00
Sebastien Bourdeauducq 4164fb4ac9 bus/csr: configurable data width 2012-08-26 21:19:34 +02:00
Florent Kermarrec a99a902fef add vcd generator 2012-08-26 20:56:56 +02:00
Florent Kermarrec 97cca81e0c tb_TriggerCsr.py : use truth table generator for Sum Lut 2012-08-26 15:44:43 +02:00
Florent Kermarrec 68750445cd add truth table generator 2012-08-26 15:15:44 +02:00
Florent Kermarrec bf7864104a tb_spi2Csr: Add clk_ratio 
tb_spi2Csr: Add Read
spi2Csr : fixs
 2012-08-26 13:03:11 +02:00
Florent Kermarrec 2e54001fc1 - fix Spi2Csr mistakes 2012-08-25 23:29:23 +02:00
Florent Kermarrec b5a44f2e98 add sim: tb_Spi2Csr.py (skeleton, WIP) 2012-08-25 21:53:06 +02:00
Florent Kermarrec d14ffb9146 add sim: tb_TriggerCsr.py 2012-08-25 18:46:58 +02:00
Florent Kermarrec a7d85af25b use ram for Sum 2012-08-24 00:16:00 +02:00
Florent Kermarrec f4cac2c102 Add simulation skeleton 
Remove SRLC16E, will be replaced by distributed ram
 2012-08-22 23:59:00 +02:00
Florent Kermarrec 7dd51b3d92 new library spi2Csr (skeleton) 2012-08-13 01:02:38 +02:00
Florent Kermarrec f586b13d4b add register interface to Trigger 2012-08-12 21:17:17 +02:00