dd6ca87561
Add Mercury baseboard support from Migen, import fixes.
2017-12-18 19:30:25 -05:00
4c82eb549f
build/xilinx: add support for edif/ngc files
2017-12-16 13:20:45 +01:00
b31d0f37db
cpu/picorv32: adapt to current version, some cleanup
2017-12-10 03:01:53 +01:00
4239aff68a
cpu: cleanup wrappers
2017-12-10 02:52:01 +01:00
43429560d4
soc/integration/soc_core: add integrated_rom_init to allow initializing rom with custom code
2017-12-08 10:18:01 +01:00
27d37fa95d
targets/sim: fix
2017-12-06 22:22:05 +01:00
284b16e2c1
soc/integration/soc_core: make nmi interrupt optional
2017-12-03 23:07:41 +01:00
c1eba9a6cc
soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware
2017-11-24 13:16:58 +01:00
831b489fd3
soc/interconnect/stream: fix specific cases for last/first signal in UpConverter
2017-11-23 17:58:02 +01:00
06edd9c45c
Merge pull request #36 from mattkelly/fix-readme-typo
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Fix typo in README: experimental
2017-11-08 18:51:49 -08:00
0dfeeb58f6
Fix typo in README: experimental
2017-11-08 21:42:07 -05:00
c3d902ef42
soc/software/bios/sdram: add Kintex Ultrascale support
2017-11-08 12:59:38 +01:00
dcae61b6de
README: update copyrights
2017-11-01 21:12:42 +01:00
2665a83288
soc/interconnect/stream: expose depth on SyncFIFO
2017-10-30 22:56:09 +01:00
876f3d2c8f
Merge pull request #34 from mithro/uart-irq-change
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Change the default IRQs.
2017-10-30 13:54:19 -07:00
56ef229029
Make the interrupt dicts read only.
2017-10-29 19:45:52 -07:00
295e78ee9e
Make it harder to have conflicting interrupts.
2017-10-29 19:45:52 -07:00
ff72757b87
Bump the IRQ for liteeth based targets.
2017-10-29 19:45:52 -07:00
73e0036b99
Change the default IRQs.
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* Reserve IRQ 0 to be used as a "non-maskable interrupt" (NMI) in the
future.
* Use IRQ 2 for the LiteX. This matches the standard mor1k config which
connects the UART to IRQ 2.
This change is needed for Linux running on LiteX as it gets grumpy with
using IRQ 0 for anything other other than an NMI.
2017-10-29 19:45:52 -07:00
e07bd71b16
build/xilinx: Fixing settings finding.
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* Better error messages.
* Search correct directories;
- XXX/Vivado/<version>
- XXX/<version>/ISE_DS/
2017-10-16 18:25:51 +11:00
a6958065cf
Merge pull request #32 from felixheld/fix-readme
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remove Migen as requirement for LiteX from the quick start guide
2017-10-16 15:07:49 +11:00
8d87dfba42
remove Migen as requirement for LiteX from the quick start guide
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Migen currently isn't a dependency for LiteX
2017-10-15 22:27:09 +02:00
db6c88bbef
soc/interconnect/stream: don't use reset less on last and first signals (not reseting these signals can cause troubles in some specific cases)
2017-10-12 11:30:56 +02:00
eecd6a156e
Merge pull request #31 from mithro/bios-fix
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Couple of small fixes.
2017-10-07 08:46:38 +02:00
2c013948b1
Output better error message for flash_proxy.
2017-10-07 12:14:00 +11:00
279ec488e3
bios: Print location jumping too.
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Makes it easier to understand what is happening (and that the BIOS is
jumping to the right place).
2017-10-06 20:38:44 +11:00
8152673d18
common: Compile with debugging symbols on.
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Debugging symbols are useful when using GDB :-)
2017-10-06 20:38:44 +11:00
b1b6a74170
or1k: Use EXCEPTION_STACK_SIZE of 256bytes.
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or1k defines a 128 byte "red zone" after the stack that can not be
touched by the exception handler.
We also need 128 bytes to store the 32 registers.
2017-10-06 20:38:44 +11:00
07a9df3586
bios: Declare dependency on linked in .a files.
2017-10-06 20:38:44 +11:00
d95d561737
Merge pull request #30 from cr1901/icestorm
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Add Icestorm backend and iCEStick
2017-10-04 09:47:32 +02:00
e558473119
Add iCEStick board. Tested with litescope.
2017-10-04 01:59:53 -04:00
c3383f47ba
Port IceStorm backend from Migen.
2017-10-03 22:48:44 -04:00
ba1bf20f37
soc/cores: add cordic
2017-09-29 12:07:43 +02:00
878380abba
Merge pull request #28 from enjoy-digital/eb-docs-2
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More docs for etherbone packet fields.
2017-09-26 12:33:57 +02:00
e42ab27f30
gen/fhdl/verilog: revert _printcomb_simulation and _printcomb_regular (needed for icarus simulation) and add Finish command
2017-09-13 13:47:25 +02:00
2a8f6edded
soc/integration/soc_core: add ident_version parameter to allow adding soc version to identifier
2017-09-06 15:39:54 +02:00
3a656c61d9
More docs for etherbone packet fields.
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Info comes from http://www.ohwr.org/attachments/1669/spec.pdf dated 24 July 2012
2017-09-01 23:57:34 +10:00
797a91270f
Merge pull request #27 from enjoy-digital/etherbone-docs
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Adding a little docs to field descriptions.
2017-09-01 15:54:38 +02:00
c125ea6440
Adding a little docs to field descriptions.
2017-09-01 23:27:58 +10:00
8f3dcf90ab
soc/software/bios/sdram: add optional memtest debug traces
2017-08-18 09:42:27 +02:00
c02de1632b
soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists
2017-07-27 18:22:01 +02:00
04646b24ed
soc/interconnect/stream: fix make_m2s for reset_less
2017-07-24 18:18:35 +02:00
9509d9e361
gen/genlib/cdc/gearbox: fix possible pointers overlap by removing AsyncResetSynchronizers.
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read/write clocks don't have the same frequencies, using AsyncResetSynchronizers cause differents delay when releasing reset and can cause pointers overlap.
2017-07-24 13:39:08 +02:00
f25e46c428
Merge pull request #26 from q3k/diamond-linux-support
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Add Diamond toolchain support for Linux.
2017-07-20 14:41:05 +02:00
503df5e93e
Add Diamond toolchain support for Linux.
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This tries to replicate the same setup as in the Windows buildsystem. We
also remove the Jedecgen step, as it doesn't seem to be supported nor
necessary in newer versions of Diamond.
2017-07-20 13:21:10 +01:00
756554371a
soc/tools/remote/litex_server: allow multiple instance of server
2017-07-19 21:18:12 +02:00
0b6d38abe9
build/xilinx/programmer: add multi jtag devices support to VivadoProgrammer
2017-07-19 14:54:19 +02:00
d05d170b75
soc/integration/cpu_interface: do not generate constant access functions when with_access_functions is set to False
2017-07-19 12:18:35 +02:00
20c859d45c
soc/tools/remote/etherbone: speed optimization (~20/30%)
2017-07-17 00:25:58 +02:00
bdea4152e3
soc/core/uart: add UartStub to enable fast simulation with cpu
2017-07-06 19:19:10 +02:00
William D. Jones
Florent Kermarrec
Tim Ansell
Matt Kelly
Felix Held
Sergiusz Bazanski