Commit Graph

4848 Commits

Author SHA1 Message Date
Florent Kermarrec 8d90f4e97b build/xilinx/vivado: use VHDL 2008 as default 2019-12-03 15:27:20 +01:00
Florent Kermarrec cfd17321e2 targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed) 2019-12-03 10:11:15 +01:00
Florent Kermarrec 201d60f37a targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16) 2019-12-03 09:05:52 +01:00
Florent Kermarrec 6b82064723 targets: uniformize, improve presentation 2019-12-03 08:58:01 +01:00
Florent Kermarrec 718f69953b README: fix LitePCIe Travis-CI link 2019-12-02 11:03:42 +01:00
Florent Kermarrec 6de20f185a soc/interconnect/csr: add fields support for CSRStorage's write simulation method 2019-12-02 09:44:44 +01:00
Florent Kermarrec 2567a0ae1d soc/cores/gpio: add GPIO Tristate 2019-12-01 21:26:37 +01:00
Florent Kermarrec d702c0fe35 setup.py: update long_description 2019-11-30 19:30:50 +01:00
Florent Kermarrec c9665aed38 README.md: use litex logo 2019-11-30 19:23:34 +01:00
Florent Kermarrec 82819dd536 README: switch to Markdown 2019-11-30 19:18:47 +01:00
Tim Ansell 90f9ffc505
Merge pull request #311 from kbeckmann/trellis_cabga256
trellis: Support the CABGA256 package
2019-11-29 19:05:56 -08:00
Konrad Beckmann f411d6d362 trellis: Support the CABGA256 package 2019-11-30 02:50:41 +01:00
Miodrag Milanovic 783dfa508c Properly select family for those currently supported 2019-11-29 19:11:22 +01:00
Miodrag Milanovic 6560911df2 Integrate with latest yosys changes 2019-11-29 17:12:08 +01:00
enjoy-digital 3d20442f6f
Merge pull request #310 from xobs/spi-flash-mode3-doc
spi_flash: correct documentation on SPI mode
2019-11-25 21:01:17 +01:00
Sean Cross 581c23725e spi_flash: correct documentation on SPI mode
The SPI mode is actually mode3, since the output value is updated on the
falling edge of CLK and the input value is updated on the rising edge.

This also clarifies some of the documentation based on experience with
the core.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-25 12:35:13 +08:00
Florent Kermarrec de205d4a84 tools/remote/comm_udp: only use one socket 2019-11-22 15:28:35 +01:00
Florent Kermarrec bdaca40fe4 build/generic_platform: avoid duplicate in GenericPlatform.sources 2019-11-22 15:28:07 +01:00
Florent Kermarrec 6883a43680 soc/cores/clock: change drp_locked to CSRStatus and connect it :) 2019-11-20 19:37:16 +01:00
Florent Kermarrec 36107cdfd7 soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal 2019-11-20 19:24:40 +01:00
enjoy-digital e8e70b164a
Merge pull request #309 from antmicro/mmcm-fix
soc/cores/clock: add lock reg and assign reset
2019-11-20 19:20:15 +01:00
Pawel Czarnecki fd14b76594 soc/cores/clock: add lock reg and assign reset
It was necessary to add drp_locked CSR for reading LOCK signal from
MMCM. Additionally, input signal RESET from MMCM was not driven by
any signal to do a proper reset of MMCM module thus it was impossible
to perform entirely correct dynamic clock reconfiguration.
2019-11-20 16:22:49 +01:00
Florent Kermarrec 04017519c8 soc/interconnect/axi: add Wishbone2AXILite 2019-11-20 12:32:22 +01:00
Florent Kermarrec 4b073a440a test/test_axi: cosmetic 2019-11-20 11:22:39 +01:00
Florent Kermarrec d905521185 build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository 2019-11-19 09:11:11 +01:00
enjoy-digital 02bfda5e38
Merge pull request #308 from gsomlo/gls-sdram-init
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
2019-11-18 18:24:35 +01:00
Gabriel Somlo 3ef13fd27a soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
Enable SDRAM to be initialized when csr_data_width > 8 bits.
Currently, csr_data_width up to 32 bits is supported.

Read leveling tested with csr_data_width [8, 16, 32] on the
ecp5-versa5g and trellisboard (using yosys/trellis/nextpnr),
and on the nexys4ddr (using Vivado).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-18 09:00:19 -05:00
Florent Kermarrec 1efb18f1ea soc/interconnect/packet/Depacketizer: another simplifcation pass 2019-11-18 09:06:56 +01:00
Florent Kermarrec af52203c00 soc/interconnect/packet/Depacketizer: cleanup "ALIGNED-DATA-COPY" state 2019-11-17 11:57:14 +01:00
Florent Kermarrec 8272a00d6e soc/interconnect/packet/Depacketizer: replace no_payload with sink_d.last 2019-11-17 11:50:09 +01:00
Florent Kermarrec 6059712794 test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer 2019-11-16 14:39:18 +01:00
Florent Kermarrec 9642893371 test/test_packet: add randomness on valid input, fix corner-cases on Packetizer 2019-11-16 08:49:04 +01:00
enjoy-digital 888fd55bd8
Merge pull request #307 from sergachev/master
change >512 B CSR memory exception to a warning
2019-11-15 18:17:35 +01:00
Florent Kermarrec 2f2cfc9951 soc/interconnect/packet: fix synthesis (synthesis tools can do all sort of optimizations, but we still need to provide valid verilog :)) 2019-11-15 16:19:05 +01:00
Ilia Sergachev 444ae951e9 change >512 B CSR memory exception to a warning 2019-11-15 15:34:12 +01:00
Florent Kermarrec 31661e9e2d soc/interconnect/packet: connect error/last_be only present on both sink and source 2019-11-15 14:57:31 +01:00
Florent Kermarrec 2946581e50 soc/interconnect/packet: simplify/refactor Packetizer/Depacketizer to keep it simple
To avoid complex FSMs, let the synthesis tool do the simplifications when the FSM states are not reachable.
2019-11-15 14:39:55 +01:00
Florent Kermarrec 33c4d961b5 test/test_packet: add 32/64/128-bit loopback tests (passing :)) 2019-11-15 11:37:52 +01:00
Florent Kermarrec 824faf9722 test/test_packet: prepare for testing dw > 8-bit 2019-11-15 11:32:42 +01:00
Florent Kermarrec 86662b54d0 soc/interconnect/packet: update copyright 2019-11-15 11:25:38 +01:00
Vamsi K Vytla 5c19b133ac soc/interconnect/packet: add > 8-bit support to Packetizer/Depacketizer
With high speed link (10gbps XGMII ethernet for example), stream data_width is generally
> 8-bit which make header/data un-aligned on bytes boundaries. The change allows the
Packetizer/Depacketizer to work on stream with a data_width > 8-bit.
2019-11-15 11:24:17 +01:00
Florent Kermarrec 5f151152ca build/sim: cleanup run_as_root 2019-11-15 10:57:31 +01:00
Vamsi K Vytla 446ae57b75 build/sim/modules: add XGMII 10Gbps ethernet module
Used to simulate SoCs with XGMII 10Gbps ethernet and to do LiteEth verification
2019-11-15 10:51:55 +01:00
Florent Kermarrec 56fbd2f250 sim/ethernet: remove trailing whitespaces 2019-11-15 10:39:49 +01:00
Florent Kermarrec 442e23d7fd test: add initial test_packet
Use a header with 8,16,32,64,128-bit fields and test a Packetizer/Depacketizer loopback with random field values, random packet data & length.
2019-11-15 10:29:50 +01:00
Florent Kermarrec eb3888f68e tools/litex_sim: cleanup/update (no functional change) 2019-11-14 11:19:23 +01:00
Florent Kermarrec 4798d6b750 tools/litex_term: remove automatic reboot when flashing and clear mem_regions to avoid re-flashing on next reboot(s) 2019-11-11 18:38:10 +01:00
Florent Kermarrec a17e307acf bios/flash: minor cleanup on serialboot flashing, add flash address support 2019-11-09 00:05:36 +01:00
enjoy-digital 2d6100bdbe
Merge pull request #305 from FrankBuss/master
adding support to flash an FBI image
2019-11-08 23:51:49 +01:00
Florent Kermarrec 05e8abfee3 soc_core: add integrated-rom-file parameter to allow initializing rom from command line 2019-11-08 23:32:10 +01:00