58 commits

Author	SHA1	Message	Date
Florent Kermarrec	22507b117c	bank: add re to CSRStorage ... being able to know when a register is updated is useful in many cases and avoid having to handle another register for that. re is asserted when the the last CSR of the Compound is written. Software must also write Compound in the right order.	2014-10-16 17:43:41 +08:00
Florent Kermarrec	70a2ee4368	migen/bank/description: add reset parameter to CSRStatus	2014-06-15 23:54:38 +02:00
Sebastien Bourdeauducq	8f69d9b669	bank/eventmanager: add SharedIRQ	2014-01-06 22:13:06 +01:00
Sebastien Bourdeauducq	f658802ff8	replace use of __dict__ with dir()/xdir()	2013-11-02 16:03:47 +01:00
Sebastien Bourdeauducq	0e195da3c0	bank/csrgen: add get_offset function to pre-calculate register addresses	2013-08-02 23:05:54 +02:00
Sebastien Bourdeauducq	2a296aced7	bank/description/AutoCSR: prefix csr/mem only once	2013-08-02 23:05:21 +02:00
Sebastien Bourdeauducq	246b860a85	csr: new data width API	2013-07-28 16:33:36 +02:00
Sebastien Bourdeauducq	70ffe86356	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq	c82b53f1cd	bank/description/AutoCSR: add autocsr_exclude	2013-05-08 20:58:57 +02:00
Sebastien Bourdeauducq	b9b6df6f29	bank/eventmanager: refactor, rename EventSourceLevel -> EventSourceProcess, add fully externally controlled event source	2013-05-08 18:12:26 +02:00
Sebastien Bourdeauducq	b5b29f6d5d	bank/description/CSRStorage: set reset property of storage for use in test benches	2013-05-02 11:49:23 +02:00
Sebastien Bourdeauducq	dc0304a87b	bank/description/CSRStorage: support alignment bits	2013-04-30 18:53:40 +02:00
Sebastien Bourdeauducq	c4f4143591	New CSR API	2013-03-30 17:28:41 +01:00
Sebastien Bourdeauducq	c4c4765a4e	bank/csrgen/BankArray: retain name information	2013-03-25 14:44:15 +01:00
Sebastien Bourdeauducq	53edc3557e	bank/description/Register: add get_size	2013-03-25 14:43:44 +01:00
Sebastien Bourdeauducq	fc883198ae	bank/csrgen/BankArray: create banks in sorted order	2013-03-13 23:07:44 +01:00
Sebastien Bourdeauducq	52d13959f2	bank/description: modify reg/mem in-place	2013-03-13 19:46:34 +01:00
Sebastien Bourdeauducq	04df076fba	bank: automatic register naming	2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq	b042757187	Fix Register name conflict between Pytholite and Bank	2013-03-10 19:47:21 +01:00
Sebastien Bourdeauducq	f93695f60e	bank/eventmanager: use module and autoreg	2013-03-10 19:29:05 +01:00
Sebastien Bourdeauducq	cddbc1157d	bank/description/AutoReg: check that get_memories and get_registers are callable	2013-03-10 18:11:29 +01:00
Sebastien Bourdeauducq	68fe4c269c	bank/csrgen: BankArray	2013-03-10 00:45:16 +01:00
Sebastien Bourdeauducq	f1474420df	bank/description: AutoReg	2013-03-10 00:43:16 +01:00
Sebastien Bourdeauducq	d2cbc70190	bank/description: memprefix	2013-02-25 23:14:15 +01:00
Sebastien Bourdeauducq	f9acee4e68	corelogic -> genlib	2013-02-22 23:19:37 +01:00
Sebastien Bourdeauducq	3fae6c8f03	Do not use super()	2012-12-18 14:54:33 +01:00
Sebastien Bourdeauducq	62187aa23d	migen/bank: do not create interface in default param	2012-12-06 17:28:28 +01:00
Sebastien Bourdeauducq	e89c66bf14	bank/csrgen: interface -> bus	2012-12-06 17:15:34 +01:00
Sebastien Bourdeauducq	273d9d285b	bank/description: define reset value of read signal	2012-12-05 16:40:44 +01:00
Sebastien Bourdeauducq	50ed73c937	New specification for width and signedness	2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq	6eebfce44a	Refactor Case	2012-11-29 01:11:15 +01:00
Sebastien Bourdeauducq	fee22a4631	Remove Constant	2012-11-28 23:18:43 +01:00
Sebastien Bourdeauducq	31cdb02eff	bank/description: regprefix	2012-10-15 21:21:59 +02:00
Sebastien Bourdeauducq	85081793cf	bank: remove RE signal for field registers	2012-10-09 19:07:53 +02:00
Sebastien Bourdeauducq	e410973352	bank: support for atomic writes	2012-10-08 18:43:18 +02:00
Sebastien Bourdeauducq	4164fb4ac9	bus/csr: configurable data width	2012-08-26 21:19:34 +02:00
Sebastien Bourdeauducq	11674242c4	Use super() instead of calling parent constructors directly	2012-06-08 18:06:12 +02:00
Sebastien Bourdeauducq	493b181af1	bank/description: pad unaligned multi-word registers at the top	2012-05-21 22:55:23 +02:00
Sebastien Bourdeauducq	9449bbea0a	Add LICENSE file	2012-05-21 19:56:23 +02:00
Sebastien Bourdeauducq	b9c533be51	bank/csrgen: allow specifying existing CSR interface	2012-04-06 14:59:09 +02:00
Sebastien Bourdeauducq	d8d4e81b6e	bank/csrgen: fix RE generation	2012-02-18 18:56:18 +01:00
Sebastien Bourdeauducq	55a265d967	bank: add RE signal for registers made of fields	2012-02-17 23:52:06 +01:00
Sebastien Bourdeauducq	ef7aea0f31	bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY	2012-02-15 18:23:31 +01:00
Sebastien Bourdeauducq	91e279ee04	bank/csrgen: use new bus API	2012-02-15 16:42:17 +01:00
Sebastien Bourdeauducq	0c214b484e	Use double quotes for all strings	2012-02-14 13:12:43 +01:00
Sebastien Bourdeauducq	8a61d9d121	bus/csr: Rename a->adr d->dat to be consistent with the other buses	2012-02-13 21:46:39 +01:00
Sebastien Bourdeauducq	fcd6583cbb	bank: event manager	2012-02-06 17:39:32 +01:00
Sebastien Bourdeauducq	3a2a0c4dd8	bank: support registers larger than the bus word width	2012-02-06 16:15:27 +01:00
Sebastien Bourdeauducq	f3ddfffc47	bank: refactoring	2012-02-06 13:55:50 +01:00
Sebastien Bourdeauducq	1a86f26a66	bank/csrgen: use enumerate	2012-02-06 11:18:30 +01:00