Florent Kermarrec
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a874f85854
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litescope: use CRG from Migen
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2015-03-17 11:52:54 +01:00 |
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Florent Kermarrec
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52f1c45407
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LiteXXX cores: fix test_reg.py
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2015-03-04 23:13:14 +01:00 |
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Florent Kermarrec
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1d4dc45436
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LiteXXX cores: use format in prints
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2015-03-03 10:29:28 +01:00 |
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Florent Kermarrec
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096e95cb59
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uart: use data instead of d on endpoint's layouts (coherency with others cores)
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2015-03-01 16:56:48 +01:00 |
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Florent Kermarrec
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649cdeb265
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liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
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2015-03-01 16:48:41 +01:00 |
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Florent Kermarrec
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c21a7956c8
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liteXXX cores: remove Identifier duplication
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2015-03-01 11:24:58 +01:00 |
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Florent Kermarrec
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67ca0da1d9
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liteXXX cores: share same methodology for on-board tests
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2015-03-01 11:21:12 +01:00 |
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Florent Kermarrec
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32fce11edf
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litescope: avoid uart code duplication
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2015-03-01 10:07:55 +01:00 |
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Florent Kermarrec
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b32a0e6f9e
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liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
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2015-02-28 23:33:00 +01:00 |
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Florent Kermarrec
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b34be816ec
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liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
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2015-02-28 22:23:48 +01:00 |
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Florent Kermarrec
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5c43d4d091
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litescope: create example design derived from SoC that can be used on all targets
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2015-02-28 22:19:24 +01:00 |
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Florent Kermarrec
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0fd1b9df8d
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liteXXX cores: remove redefinition of get_csr_csv
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2015-02-28 21:45:05 +01:00 |
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Florent Kermarrec
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5bd1ab7fa1
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liteXXX cores: update README and doc
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2015-02-28 21:40:59 +01:00 |
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Florent Kermarrec
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69e869893d
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remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |
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Florent Kermarrec
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df0ba1b03c
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litescope: create example_designs directory
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2015-02-28 10:42:12 +01:00 |
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Florent Kermarrec
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c4ebf244a1
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litescope: move files and modify import to misoclib.tools.litescope
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2015-02-28 10:33:46 +01:00 |
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Florent Kermarrec
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b274e948dc
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merge litescope
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2015-02-28 10:24:49 +01:00 |