8574c62f75
targets/versa_ecp5: increase sys_clk_freq to 50MHz
2018-11-12 10:12:10 +01:00
a752dafb14
targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
2018-11-12 09:45:59 +01:00
87c7d23d16
targets/ulx3s: for now revert to 25MHz clock/no pll
2018-11-12 09:44:32 +01:00
d1baae36a6
platforms/versa_ecp5: add ecp5 soc hat ios
2018-11-12 09:43:31 +01:00
b3bf1c9517
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-12 08:12:07 +01:00
1be6762dfe
Merge pull request #125 from daveshah1/trellis_sdram
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ecp5 soc hat wip
2018-11-12 08:11:57 +01:00
425ad755ec
plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5
2018-11-12 08:06:22 +01:00
c57aa545ca
targets/ulx3s: get memtest working by disabling sdram refresh
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Will need to be fixed...
2018-11-09 18:40:14 +01:00
9a6447172a
soc/integration/soc_sdram: allow using axi interface with litedram
2018-11-09 15:42:34 +01:00
416bdb6483
boards/platforms: add avalanche polarfire board ios definition
2018-11-08 18:24:12 +01:00
f08f80bed1
working on Versa-5G dram
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-06 14:39:25 +00:00
fc0d5c3963
bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients
2018-11-05 18:44:28 +01:00
09f962fdc4
target/kcu105: add reset button
2018-11-05 18:41:49 +01:00
169f8d8cb5
boards/platforms/kcu105: fix sdram/dq pin swap
2018-11-05 17:01:42 +01:00
d78d5d3e7f
Debugging ULX3S SDRAM
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-05 11:54:22 +00:00
2624ba48c2
bios/sdram: replace DDR3_MR1 constant with DDRX_MR1
2018-11-05 10:47:25 +01:00
6be74aa17f
boards/targets: add kcu105
2018-11-05 10:44:50 +01:00
93c623251b
Merge pull request #122 from daveshah1/trellis_ulx3s
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Switch Trellis build to use LPF constraints; working on ULX3S
2018-11-02 19:59:23 +01:00
00ef8240ef
Merge pull request #124 from jfng/master
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build/sim/verilator: don't use --threads when $(THREADS) is unset
2018-11-02 17:46:04 +01:00
dcbe759b64
build/sim/verilator: don't use --threads when $(THREADS) is unset
2018-11-02 14:22:44 +01:00
6f38213acc
boards/platforms/kc705: add user_sma_mgt_refclk
2018-11-01 10:52:01 +01:00
4cdd679908
Merge pull request #123 from cr1901/prv32-min
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PicoRV32 Enhancements
2018-11-01 10:45:32 +01:00
e56f71824d
libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time).
2018-11-01 05:02:04 -04:00
f32121e0e1
cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector.
2018-11-01 02:23:01 -04:00
77389d27b5
libbase/crt0-picorv32: Ensure BSS is cleared on boot.
2018-11-01 02:18:03 -04:00
f7969b660a
cores/clock: add with_reset parameter (default to True)
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In some cases we want to generate the reset externally.
2018-10-31 16:23:23 +01:00
0729b3a059
ulx3s: Connect SDRAM clock
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 13:29:35 +00:00
8404434956
Fix Trellis build; ULX3S demo boots to BIOS
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 12:27:05 +00:00
0c1d8d5993
trellis: Switch to using LPF for constraints
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 11:43:39 +00:00
445c49400f
boards/platforms/kcu105: add sfp_tx/rx definition
2018-10-31 10:48:48 +01:00
f69bd877b9
cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations).
2018-10-30 06:00:45 -04:00
d05fe673a0
cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs.
2018-10-30 06:00:45 -04:00
e9d4c882ba
build/lattice/prjtrellis: fix default toolchain_path
2018-10-30 10:28:12 +01:00
468780c045
soc/cores/spi_flash: add endianness parameter
2018-10-30 10:19:21 +01:00
6f3131e259
soc/interconnect/stream_packet: use reverse_bytes from litex.gen
2018-10-30 10:16:55 +01:00
b796853893
gen: add common with reverse_bits/reverse_bytes functions
2018-10-30 10:15:29 +01:00
71fc34d7b6
boards/targets/ulx3s: reduce l2_size
2018-10-30 10:14:48 +01:00
75d073f394
build/lattice/prjtrellis: fix typo
2018-10-30 10:14:30 +01:00
6048a5291c
build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts.
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nextpnr expects TRELLIS_IO on all ios, it's not possible to ensure that with a wrapper.
We now just modify the generated verilog to insert the io constraints and TRELLIS_IOs.
2018-10-30 08:54:30 +01:00
2243f628f7
build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl
2018-10-30 08:47:12 +01:00
3a8bb94ab4
Merge pull request #121 from cr1901/patch-3
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Update vivado.py
2018-10-29 20:54:23 -07:00
f3111e1142
Update vivado.py
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Fix regression which caused Vivado to not be run at all.
2018-10-29 23:43:32 -04:00
98fa899692
boards/targets: add ulx3s
2018-10-29 19:24:28 +01:00
7d779473f1
boards/platforms: add ulx3s
2018-10-29 19:23:59 +01:00
d9dcad33a4
build/lattice/prjtrellis: add inout support
2018-10-29 19:23:21 +01:00
091ad799b0
build/lattice/common: add tristate support
2018-10-29 19:22:04 +01:00
23acefb14e
boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed
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simple.py configuration tested:
python3 simple.py --cpu-type=lm32 --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
python3 simple.py --cpu-type=vexriscv --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
2018-10-29 16:02:25 +01:00
1097f82283
build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis"
2018-10-29 15:58:54 +01:00
52917a710e
boards/targets/simple: add gateware-toolchain parameter
2018-10-29 15:56:46 +01:00
d84083f642
boards/platforms/versaecp55g: use ftdi serial pins
2018-10-29 15:39:51 +01:00
Florent Kermarrec
David Shah
Jean-François Nguyen
William D. Jones
Tim Ansell