Only use input clock divisors which respect the device limitation for
the phase-frequency detector's input frequency. This avoids errors where
Quartus complains the PLL parameters are invalid and refuses to
implement it.
The supported PFD frequencies in integer mode have been verified against
each family's datasheet. The unsupported-by-LiteX fractional frequency
information is removed for clarity.
As a bonus, this speeds up PLL config computation by several times.
This fixes two issues that prevented clock constraints (e.g.
"add_false_path_constraint") from working properly in Quartus.
The first fix passes the "keep" synthesis attribute through to the
generated Verilog in a way Quartus can understand.
The second fix tells Quartus to name PLL clocks according to their net
instead of the physical pin name by passing the "use_net_name" flag to
"derive_pll_clocks" in the .sdc file. Combined with the above, PLL
clocks will now be named according to the kept net.
This fix has been verified on Quartus Prime Lite 20.1.1.720.
An earlier patch fixed the swapped red and blue channels on the HDMI
PHYs. This exposed the fact that the framebuffer readout was swapped
too.
The framebuffer readout is fixed by this patch to match the r5g6b5 and
a8b8g8r8 color format definitions documented in the Linux kernel's
simplefb driver and used by LiteX:
https://www.kernel.org/doc/Documentation/devicetree/bindings/display/simple-framebuffer.txt
This has been tested using 16 bit SDRAM in both supported color formats.
Additionally the green color used by the video terminal is swapped. It
now matches the color used by LiteX on Ubuntu's terminal, from which it
was probably originally sourced.
Allows different update strategies which I find useful.
The git update process now checks the return code! So that problems in the update process can be noticed.
The `fulld` and `fullq` variants point to the wrong (`LitexFullConfig`)
verilog. Fix by pointing to the correct code (`LitexFullDConfig` and
`LitexFullQConfig`, respectively).
Reported-by: Ioannis Ioannou <roryt@roryt.gr>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Add "flow3" option to abc9 mode. This runs FPGA mapping several times,
producing a generally better mapping at the cost of increased runtime
(see https://github.com/Ravenslofty/yosys-cookbook/blob/master/ecp5.md).
Also, add a "--yosys-flow3" build option to both "trellis" and "oxide".
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
enjoy-digital
Gwenhael Goavec-Merou
Thomas Watson
Dolu1990
Christian Klarhorst
Gabriel Somlo
Maciej Kurc