FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
Simulate a Rocket-based 64-bit LiteX SoC with the following command:
litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket
NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
After LiteDRAM commit #50e1d478, an additional positional argument
('databits') is required by the PhySettings() constructor.
The value used here (32) will generate a 64MByte simulated SDRAM.
When we get an error with errno 13, it means that the user doesn't
have access to the USB device. Rather than silently eating this
error and returning -1, print out a message to aid in debugging.
Signed-off-by: Sean Cross <sean@xobs.io>
The previous value -- 0xc0 -- is used by Windows all the time to query
special descriptors. This was causing a conflict when using the USB
bridge on a Windows device.
Change the magic packet from "Vendor: Device" queries to "Vendor:
Other" by setting the bottom two bits.
Signed-off-by: Sean Cross <sean@xobs.io>
This could be useful in specific case were we don't have a wishbone master
but just want to have a csr bus and allow the user to define it.
/!\ Since there is no arbitration on between the CSR masters, use this with
precaution /!\
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
The CPUs can now reserve specific interrupts with reserved_interrupts property.
User can still define interrupts in SoCCore.interrupt_map (old way) or use
add_interrupt method. Interrupts specific to SoCCore internal modules are
allocated automatically on the remaining free interrupt ids.
Priority for the interrupts allocation:
- 1) CPU reserved interrupts.
- 2) User interrupts.
- 3) SoCCore interrupts.
Gabriel L. Somlo
Florent Kermarrec
Tim Ansell
Antony Pavlov
Sean Cross
Mateusz Holenko