Sebastien Bourdeauducq
|
7d18736ff2
|
Update gitignore
|
2012-05-17 01:42:08 +02:00 |
|
Sebastien Bourdeauducq
|
79124d822b
|
Identifier
|
2012-05-17 01:41:41 +02:00 |
|
Sebastien Bourdeauducq
|
141269b384
|
Get CSR base addresses from include file
|
2012-05-16 10:36:46 +02:00 |
|
Sebastien Bourdeauducq
|
bb798176fc
|
Common include files
|
2012-05-16 10:20:04 +02:00 |
|
Sebastien Bourdeauducq
|
b6aa40d845
|
bios: automatically enable hardware memory controller and test memory
|
2012-05-15 19:29:26 +02:00 |
|
Sebastien Bourdeauducq
|
68cd445662
|
bus/wishbone2asmi: fix cache tag size
|
2012-05-15 15:18:03 +02:00 |
|
Sebastien Bourdeauducq
|
0bea1e2589
|
asmi: dat_wm high to disable data write
|
2012-05-15 14:41:54 +02:00 |
|
Sebastien Bourdeauducq
|
425c8b8e70
|
asmicon/multiplexer: fix read tag delay
|
2012-05-15 13:13:40 +02:00 |
|
Sebastien Bourdeauducq
|
7ecfd60368
|
bios: more DDR diagnostic functions
|
2012-05-14 20:07:57 +02:00 |
|
Sebastien Bourdeauducq
|
2ccdade88e
|
tb/asmicon_wb: better access pattern
|
2012-04-30 19:08:31 -05:00 |
|
Sebastien Bourdeauducq
|
f2c20e4af0
|
bus/asmibus/hub: hack to prevent comb loops
|
2012-04-30 17:11:42 -05:00 |
|
Sebastien Bourdeauducq
|
398ece8fe2
|
fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
|
2012-04-30 16:38:40 -05:00 |
|
Sebastien Bourdeauducq
|
0b62e573ae
|
sim: pass extra keyword arguments to Verilog converter
|
2012-04-30 16:38:17 -05:00 |
|
Sebastien Bourdeauducq
|
87ee4baaf0
|
tb/asmicon_wb: test asmicon with wishbone bridge
|
2012-04-26 17:53:05 -05:00 |
|
Sebastien Bourdeauducq
|
902908bd3b
|
tb/asmicon: do not keep files
|
2012-04-26 17:21:10 -05:00 |
|
Sebastien Bourdeauducq
|
6a52e44d09
|
fhdl: support len() on signals
|
2012-04-08 18:06:22 +02:00 |
|
Sebastien Bourdeauducq
|
b9c533be51
|
bank/csrgen: allow specifying existing CSR interface
|
2012-04-06 14:59:09 +02:00 |
Brandon Hamilton
|
49b58a03a0
|
Optionally accept iverilog simulator options
|
2012-04-03 12:58:19 +02:00 |
|
Sebastien Bourdeauducq
|
19b1cc2529
|
Remove uses of pads, new constraints system
|
2012-04-02 19:22:17 +02:00 |
|
Sebastien Bourdeauducq
|
2a4e49e381
|
fhdl: phase out pads
|
2012-04-02 19:21:43 +02:00 |
|
Sebastien Bourdeauducq
|
1b60c7ff40
|
vpi: delete merged Icarus Verilog patch
|
2012-04-02 19:11:32 +02:00 |
|
Sebastien Bourdeauducq
|
623e8e436a
|
fhdl/verilog: do not attempt to initialize instance and mem output signals
|
2012-04-02 12:59:42 +02:00 |
|
Sebastien Bourdeauducq
|
d2c4afe66c
|
asmicon: various fixes. Now produces convincing refresh/read sequences.
|
2012-04-01 23:24:24 +02:00 |
|
Sebastien Bourdeauducq
|
f5671c566f
|
tb/asmicon: global test bench
|
2012-04-01 23:23:45 +02:00 |
|
Sebastien Bourdeauducq
|
6e3b25ebb6
|
bus/dfi: reset active low signals to 1
|
2012-04-01 17:43:24 +02:00 |
|
Sebastien Bourdeauducq
|
d3c6b8d16f
|
sim/proxy: support lists
|
2012-04-01 17:19:53 +02:00 |
|
Sebastien Bourdeauducq
|
f3ae22f488
|
fhdl/verilog: initialize internal read-only signals with their reset values
|
2012-04-01 16:39:11 +02:00 |
|
Sebastien Bourdeauducq
|
185bd66ee4
|
tb/asmicon: bankmachine test bench
|
2012-03-31 18:11:29 +02:00 |
|
Sebastien Bourdeauducq
|
0dfc215fe8
|
corelogic/roundrobin: handle correctly special case with 1 request source
|
2012-03-31 18:01:40 +02:00 |
|
Sebastien Bourdeauducq
|
b1e5b9ef36
|
tb/asmicon/bankmachine: test buffer and NACK
|
2012-03-31 10:06:44 +02:00 |
|
Sebastien Bourdeauducq
|
c129c98e10
|
tb/asmicon/bankmachine: selector test bench
|
2012-03-31 09:56:22 +02:00 |
|
Sebastien Bourdeauducq
|
ac7d89a4fe
|
asmicon/bankmachine: fixes
|
2012-03-31 09:55:52 +02:00 |
|
Sebastien Bourdeauducq
|
94b02aa8ed
|
bus/asmicon: initiator
|
2012-03-30 22:16:31 +02:00 |
|
Sebastien Bourdeauducq
|
bccc5f5c21
|
tb: remove obsolete norflash test bench
|
2012-03-30 16:41:12 +02:00 |
|
Sebastien Bourdeauducq
|
c6a4a8f462
|
tb/asmicon: refresher test
|
2012-03-30 16:40:51 +02:00 |
|
Sebastien Bourdeauducq
|
bb864c65dc
|
sim: proxy
|
2012-03-30 16:40:26 +02:00 |
|
Sebastien Bourdeauducq
|
cd82f16806
|
asmicon/refresher: fix refresh sequence done signal
|
2012-03-30 16:26:50 +02:00 |
|
Sebastien Bourdeauducq
|
081b658e2d
|
Update copyright notices
|
2012-03-23 16:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
ab799b874f
|
tools: new flterm
|
2012-03-21 09:11:43 +01:00 |
|
Sebastien Bourdeauducq
|
d47b564fad
|
corelogic/fsm: typo
|
2012-03-18 22:12:46 +01:00 |
|
Sebastien Bourdeauducq
|
c26efa28ca
|
asmicon: multiplexer (untested)
|
2012-03-18 22:11:01 +01:00 |
|
Sebastien Bourdeauducq
|
0e00837f42
|
asmicon: move slot time to timing settings
|
2012-03-18 14:57:31 +01:00 |
|
Sebastien Bourdeauducq
|
b1eb919ad2
|
asmicon: bank machine (untested)
|
2012-03-18 00:12:03 +01:00 |
|
Sebastien Bourdeauducq
|
5f28103769
|
corelogic/fsm: delayed enters
|
2012-03-18 00:09:40 +01:00 |
|
Sebastien Bourdeauducq
|
a4294762d0
|
corelogic/roundrobin: CE switching
|
2012-03-16 16:54:47 +01:00 |
|
Sebastien Bourdeauducq
|
7c377880fa
|
asmicon: refresher (untested)
|
2012-03-15 20:29:26 +01:00 |
|
Sebastien Bourdeauducq
|
e3ef121440
|
norflash: use new timeline API
|
2012-03-15 20:26:04 +01:00 |
|
Sebastien Bourdeauducq
|
e969b9afc3
|
corelogic: convert timeline to function and move to misc
|
2012-03-15 20:25:44 +01:00 |
|
Sebastien Bourdeauducq
|
7b14e0bd05
|
asmicon: skeleton
|
2012-03-14 18:26:05 +01:00 |
|
Sebastien Bourdeauducq
|
1665f293a6
|
bus/asmibus/hub: require finalization before get_slots
|
2012-03-14 16:19:29 +01:00 |