29bb397bb6
soc/integration/export: Add parameter to enable/disable fields access function generation.
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Fields access function have been contributed and probably used by a few project but not really
by LiteX projects or cores itselves.
This generates complex code and compilation warnings, so it can be useful to disable them by default (but still allow used to enable them).
2024-05-14 11:22:46 +02:00
9f4bd5cec8
integration/export: Split get_csr_header in simpler functions.
2024-05-14 11:00:41 +02:00
c42cc350c6
integration/export: Split _get_rw_functions_c in simpler functions.
2024-05-14 10:47:38 +02:00
2613ae606a
interconnect/packet/Status: Simplify logic.
2024-05-13 17:52:24 +02:00
8b175c2575
CHANGES: Update.
2024-05-13 16:33:11 +02:00
0d3a8220dd
Merge pull request #1948 from Liamolucko/riscv-triples
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Add missing 32-bit variants of RISC-V target triples
2024-05-07 15:15:09 +02:00
b61e8b5d42
Merge pull request #1945 from Nicolas-Gaudin/master
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Support isr for cv32e41p core
2024-05-07 15:13:44 +02:00
e4cfe87109
Merge pull request #1946 from nrndda/AXILite_LitexXModule_revert
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Revert LitexModule for AXILiteSRAM as well.
2024-05-07 15:10:55 +02:00
86a43c9ff7
integration/export: Fix get_csr_header/base_define when with_csr_base_define is set to False.
2024-05-06 14:59:17 +02:00
e07c4fdb2a
Add missing 32-bit variants of RISC-V target triples
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I had to waste another 10-15 minutes building a `riscv64-none-elf` GCC
instead after LiteX didn't like my `riscv32-none-elf` one, so I thought
I'd quickly add it. (I was using that target triple because it's what
Nix's `pkgsCross.riscv32-embedded` package set uses).
I also added 32-bit variants of the rest of the target triples which
didn't have them.
2024-05-04 17:41:32 +10:00
26f5e8a149
Revert LitexModule for AXILiteSRAM as well. Follows revert d021564fca for wishbobe.
2024-05-03 00:51:01 +03:00
bd0adb5be7
Support isr for cv32e41p core
2024-04-30 14:07:07 +02:00
76a704377f
Merge pull request #1941 from motec-research/vexriscv_debug_halted
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cpu/vexriscv: expose o_halted
2024-04-26 13:43:40 +02:00
7aae2bf897
Merge pull request #1940 from enjoy-digital/Dolu1990-patch-1
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cpu/naxriscv update mBus to preserve memory accesses offset
2024-04-26 11:21:18 +02:00
fd477703db
soc/integration/export: Revert #1938 (needs to be reviewed/discussed).
2024-04-26 10:59:02 +02:00
bd4ca4371d
Merge pull request #1938 from motec-research/guard_access_function
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soc/export: add guard for access_functions
2024-04-26 12:06:49 +10:00
3a008b4988
cpu/vexriscv: expose o_halted
2024-04-26 11:17:41 +10:00
ea33e37b1a
cpu/naxriscv update mBus to preserve memory accesses offset
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See #1922
2024-04-25 16:06:34 +02:00
b6bfe42b6b
Merge pull request #1937 from motec-research/litex_term_deprecation_warning
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tools/litex_term: fix DeprecationWarning
2024-04-25 11:38:09 +02:00
ac1166946c
Merge pull request #1936 from motec-research/fix_recursive_exception
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get_data_mod(): fix recursive exception reporting
2024-04-25 11:37:41 +02:00
546f4d93ff
Merge pull request #1939 from hansfbaier/master
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yosys+nextpnr: fix error message
2024-04-25 07:03:44 +02:00
d73190ac29
yosys+nextpnr: fix error message
2024-04-25 06:23:22 +07:00
7481b1e161
soc/export: add guard for access_functions
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Disable access functions with -DLITEX_ACCESS_FUNCTIONS=0 when compiling.
Useful when using litex generated headers in an environment where
the access functions generate warnings and are not used.
2024-04-22 12:16:48 +10:00
19db78da15
get_data_mod(): fix recursive exception reporting
2024-04-22 12:09:45 +10:00
60d9a635ce
tools/litex_term: fix DeprecationWarning
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litex/litex/tools/litex_term.py:557: DeprecationWarning: setDaemon() is deprecated, set the daemon attribute instead
self.reader_thread.setDaemon(True)
litex/litex/tools/litex_term.py:586: DeprecationWarning: setDaemon() is deprecated, set the daemon attribute instead
self.writer_thread.setDaemon(True)
2024-04-22 11:43:17 +10:00
d324c0e150
test/test_cpu: Disable Microwatt that seems to be broken.
2024-04-20 08:51:10 +02:00
e4dc68206d
Merge pull request #1932 from trabucayre/fix_openxc7
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build/xilinx/yosys_nextpnr.py: fix device name for xc7a35ticsg324-1L & xc7a200t-sbg484-1 (as done for f4pga)
2024-04-19 13:43:31 +02:00
7f7e44646d
build/xilinx/yosys_nextpnr.py: fix device name for xc7a35ticsg324-1L & xc7a200t-sbg484-1 (as done for f4pga)
2024-04-19 06:57:01 +02:00
d6eeb20505
tools/litex_term: Minor cosmetic changes.
2024-04-18 15:09:24 +02:00
22f4637570
Revert "Uart tx irq handling fix " (issue #554 )
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This reverts commit 6885770e47
2024-04-16 14:01:38 +02:00
3978af9c39
test/test_hyperbus: Update.
2024-04-16 11:12:30 +02:00
a44b7944ca
CHANGES: Update.
2024-04-16 10:51:19 +02:00
fd6f913525
cores/hyperbus: Switch default latency_mode to variable.
2024-04-16 10:20:18 +02:00
62b9c64212
cores/hyperbus: Add status register to report configured latency_mode to software and allow corresponding configuration.
2024-04-16 10:18:53 +02:00
576ab24b6c
Merge pull request #1926 from enjoy-digital/hyperbus_variable_latency
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HyperRAM: Add variable latency and configuration support.
2024-04-15 17:39:04 +02:00
e3d1391487
Merge pull request #1925 from chmousset/fix_efinix_t8q144
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[fix] T8Q144 PLL input instance reference
2024-04-15 17:38:37 +02:00
ebabe82c70
software/bios/main: Rewrite HyperRAM init/config.
2024-04-15 16:03:55 +02:00
67586e8a24
cores/hyperbus: Update docstring.
2024-04-15 15:05:58 +02:00
d25fd85f55
cores/hyperbus: More cleanups.
2024-04-15 14:56:08 +02:00
2100a6bd8c
cores/hyperbus: reg_buf.source -> reg_ep.
2024-04-15 14:48:38 +02:00
1597791fb6
cores/hyperbus: Simplify reg_write/read_done.
2024-04-15 14:43:15 +02:00
8e48d0d330
cores/hyperbus: Cleanup/Improve Config/Reg Interfaces.
2024-04-15 14:33:41 +02:00
6e00cfa9d0
cores/hyperbus: Cleanup fixed/variable latency support.
2024-04-15 14:05:39 +02:00
739b66a15b
[fix] Trion T8 have a V1 PLL in BGA packages, but a V2 PLL in TQFP package. DP files varies accordingly
2024-04-15 12:09:18 +02:00
93f76ede95
bios/main: Test down to latency = 3, working.
2024-04-15 12:06:49 +02:00
a95f1b8486
cores/hyperbus: Make latency dynamically configurable.
2024-04-15 12:06:11 +02:00
6216bd4e99
cores/hyperbus: Add latency_mode parameter and test different latencies/modes in simulation.
2024-04-15 10:32:13 +02:00
33a1fcda48
software/bios: Do minimal reconfiguration for variable latency and start testing latency cycles re-configuration.
2024-04-12 19:35:31 +02:00
f8c59c03e3
cores/hyperbus: Add variable latency support (working on ti60 f225).
2024-04-12 18:50:19 +02:00
b192103822
cores/hyperbus: Fix bytes order on register writes.
2024-04-12 16:06:26 +02:00
Florent Kermarrec
Liam Murphy
Dmitry Derevyanko
Nicolas Gaudin
Dolu1990
AndrewD
Andrew Dennison
Gwenhael Goavec-Merou
Hans Baier
Charles-Henri Mousset