2ae55e8009
setup.py: add litex_jtag_uart and litex_crossover_uart to console_scripts.
2020-05-29 10:40:17 +02:00
62d939e85f
Merge pull request #543 from antmicro/jboc/eeprom-sim
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litex/build/sim: add module for simulating SPD EEPROM
2020-05-28 16:46:34 +02:00
c4f96318ec
targets/nexys4ddr: fix sdcard assert.
2020-05-28 15:31:33 +02:00
76cc112ecf
bios: add main bus and csr bus infos, use KiB/GiB.
2020-05-28 15:05:24 +02:00
a0ce4ce56b
litex/build/sim: add module for simulating SPD EEPROM
2020-05-28 12:10:25 +02:00
02072deab1
integration/soc/add_sdcard: always use 32-bit/512bytes memories (not sure this will change?) and allocate sdwrite/sdread regions dynamically.
2020-05-27 23:47:07 +02:00
4b3afa75a7
integration/soc: add add_sdcard method with integration code from nexys4ddr.
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Even if not cleaned up yet, having it there will avoid duplications in targets.
2020-05-27 23:18:15 +02:00
c78caeb998
csr: Fix definition(s) of CSR_BASE in generated headers
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CSR_BASE is currently defined twice. Once in mem.h as the base
of the CSR region in the SoC address space, and once in csr.h
as the base address for all CSRs.
This fixes two issues with those definitions:
- The mem.h one is unconditional which prevents an external
redefinition (which is useful under some circumstances such as
when using an address decoder outside of LiteX with a standalone
core).
- The csr.h one is actually the origin of the first CSR region
rather than the origin of the CSR region in the SoC space. They
are usually the same ... unless you don't have CSR bank 0 in
which case the csr.h one becomes different. This causes conflicts
with the mem.h definition and breaks projects using a standalone
cores.
The first one is fixed by adding the #ifndef/#endif around the
definition of the memory regions, the second one by passing the
csr_base to use to get_csr_header()
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-27 21:48:00 +02:00
f8bb500a43
liblitedram/sdram: Add option to disable cdelay()
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When running in sim, those delays can take a *long* time, which
isn't always necessary with the simulated litedram PHY.
This allows system.h to optionally set CONFIG_SIM_DISABLE_DELAYS
which causes cdelay to do nothing.
This is especially useful when using a verilated litedram inside
a bigger/slower simulated design as to not spend a huge amount
of time going through the initializations.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-27 21:39:28 +02:00
6d72ef28a8
cpu/serv: add variants.
2020-05-27 20:00:10 +02:00
fd7ec50e43
soc/integration/export: add optional csr_base parameter.
2020-05-27 19:59:54 +02:00
795ff08a20
build/sim/verilator: add regular_comb parameter (that defaults to False) and pass it to get_verilog.
2020-05-27 19:54:52 +02:00
25d2e7c92f
Merge pull request #542 from gsomlo/gls-sdcard-followup
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software/bios: fixup sdclk command
2020-05-27 19:04:18 +02:00
3fd6ecd86e
Merge pull request #541 from antmicro/jboc/spd-read
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Add support for I2C to read SPD EEPROM
2020-05-27 19:03:50 +02:00
68f83cbcaf
CHANGES: document deprecated/moved modules.
2020-05-27 18:46:55 +02:00
ab80606036
soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone.
2020-05-27 18:40:45 +02:00
6da98ca14d
software/bios: fixup sdclk command
2020-05-27 12:38:59 -04:00
0a3d649ad8
interconnect/wishbone: integrate Wishbone2CSR.
2020-05-27 18:15:05 +02:00
b5b88d27b5
interconnect/csr_bus: add separators.
2020-05-27 18:13:57 +02:00
86952a6e06
interconnect/wishbone: remove CSRBank (probably not used by anyone).
2020-05-27 18:04:08 +02:00
e404608cf4
interconnect/wishbone: add separators and move SDRAM/Cache.
2020-05-27 17:59:33 +02:00
1fddd0e3d3
interconnect/wishbone: simplify DownConverter.
2020-05-27 17:34:11 +02:00
1172c10afb
bios: move I2C from liblitedram to libbase
2020-05-27 15:37:19 +02:00
e0d2682055
interconnect/wishbone: remove UpConverter (probably not used by anyone and would need to be rewritten).
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We'll provide a better implementation if this is useful.
2020-05-27 15:27:33 +02:00
696b31ed18
tools/litex_sim: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-05-27 15:16:30 +02:00
2efcf87925
targets/nexys4ddr: update add_sdcard method.
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Tested with:
sdinit
sdtestwrite 0x10 foobar
sdtestread 0x10
2020-05-27 14:09:05 +02:00
472bf9ac71
bios/sdram: expose I2C functions
2020-05-27 11:56:59 +02:00
2934c085ef
CHANGES: add JTAG UART.
2020-05-27 09:00:43 +02:00
3b47d4a479
tools/litex_jtag_uart: add openocd config and telnet port parameters.
2020-05-27 08:59:12 +02:00
67cf67034c
cpus: remove common cpu variants/extensions definition and simplify variant check.
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Having common cpu variants/extensions has no real additional value since we are supporting
very various CPUs where minimal/standard/full have different meanings. Checking against
common variants/extensions has also cause more issues recently when adding new CPUs than
the additional value it was supported to provide.
So let's just simplify things: a CPU provide the supported variants and we just check
against that.
2020-05-26 09:36:44 +02:00
062ff67e12
cpu/microwatt: add standard+ghdl variant that uses GHDL Yosys plugin.
2020-05-26 08:51:33 +02:00
24687cbd9f
tools/litex_client/RemoteClient: add base_address parameter.
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Useful when address translation is done in the SoC.
2020-05-25 14:11:14 +02:00
78a9579e09
cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word.
2020-05-25 10:46:53 +02:00
370e46529d
Merge pull request #539 from dayjaby/pr-fix_uart_startbit
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Fix UART startbit: 1 cycle later
2020-05-25 10:33:58 +02:00
c75cf45ab4
tools: add litex_jtag_uart to create a virtual uart for the jtag uart.
2020-05-25 10:21:06 +02:00
2cf83b9f69
tools: rename litex_crossover poc to litex_crossover_uart, remove from setup for now.
2020-05-25 10:19:16 +02:00
e853ad4b61
fix uart startbit: 1 cycle later
2020-05-24 16:12:07 +02:00
bed5aafd6c
tools: add litex_crossover to be able to use lxterm (and serialboot) over a crossover UART (bridged over UART/Ethernet/PCIe/USB, etc...).
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This is still a proof of concept but can be used/tested with:
lxsim --with-etherbone --uart-name=crossover --csr-csv=csr.csv
lxserver --udp --udp-ip=192.168.1.51
lxcrossover (will indicate the virtual_tty)
lxterm virtual_tty
2020-05-24 10:55:25 +02:00
3833bc3ec3
litex_sim: override uart_name to sim only for serial.
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Using uart_name=crossover is useful to simulate crossover mode.
2020-05-24 09:52:56 +02:00
da7fd30847
CHANGES: update.
2020-05-23 18:56:51 +02:00
2fb52e66b1
integration/soc: remove TODO in header.
2020-05-23 18:54:04 +02:00
b65f18c357
cpu/cv32e40p: fix copyright year.
2020-05-23 18:53:03 +02:00
30f3517041
cpu/cv32e40p: add copyright and improve indentation.
2020-05-22 15:55:35 +02:00
b23702ecc4
litex_setup/pythondata-cpu-cv32e40p: clone in recursive mode.
2020-05-22 15:43:00 +02:00
4c4cd335de
Merge pull request #535 from antmicro/arty-cv32e40p
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Add support for the CV32E40P RISC-V CPU
2020-05-22 13:44:10 +02:00
7d09ea19ef
Merge pull request #538 from antmicro/fix_libbase
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libbase: Include missing uart header
2020-05-22 12:28:00 +02:00
9d16b0fc82
libbase: Include missing uart header
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This fixes compilation on mor1kx.
2020-05-22 11:43:18 +02:00
3d06dc028c
test/test_targets: update build_test.
2020-05-22 08:42:02 +02:00
bdc7eb5c48
litex_sim: load SPD data from files in hexdump format as printed in BIOS
2020-05-21 16:20:06 +02:00
a42dc97401
bios/sdram: add BIOS command for reading SPD
2020-05-21 14:32:31 +02:00
Florent Kermarrec
Jędrzej Boczar
Benjamin Herrenschmidt
Gabriel Somlo
David Jablonski
Mateusz Hołenko