2bbcc218f3
sim: fix case break
2015-10-20 17:18:33 +08:00
60ae9dce0d
sim: do not use py35 collections.Generator
2015-10-20 16:37:54 +08:00
ac5271e80e
sim: truncate case test value
2015-10-19 20:08:46 +08:00
1f89900b16
sim: generators are also iterables...
2015-10-19 19:21:20 +08:00
02d804feab
sim: accept iterables as generator list
2015-10-19 19:18:17 +08:00
0999a17319
verilog, sim: accept iterables in FHDL statements
2015-10-19 19:17:26 +08:00
a824046bbc
Revert "sim/core: fix Cat bitshift"
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This reverts commit 6d6f91a02b
2015-10-19 16:08:42 +08:00
6d6f91a02b
sim/core: fix Cat bitshift
2015-10-19 16:07:45 +08:00
28962ff438
sim/core: truncate evaluated values before test in If
2015-10-19 15:58:21 +08:00
4acb7bc662
sim: support execution of nested statement lists (typo)
2015-10-15 13:53:04 +08:00
3b7f1264f1
sim: support execution of nested statement lists
2015-10-15 13:52:24 +08:00
e0899c1424
sim: make sure replaced memory signals are always in VCD signal set
2015-10-05 12:24:32 +08:00
808cf06add
fhdl: replace flen with len
2015-09-26 18:45:10 +08:00
8534562185
sim: fix slice assign
2015-09-22 20:33:44 +08:00
2c1553fea2
sim: insert resets, support ClockSignal and ResetSignal
2015-09-21 22:13:36 +08:00
99af825a5a
sim: drive clock signals
2015-09-21 21:53:41 +08:00
a67b4baa0c
sim: VCD output support
2015-09-21 21:20:31 +08:00
f1dc008d32
Simulator will be rewritten
2015-09-05 15:07:00 -06:00
76302d7aa6
vpi: cleanup (thanks sb)
2015-05-13 10:13:14 +02:00
98cf103c65
vpi: fix and simplify windows simulation (ends of msg were ignored)
2015-05-13 03:03:34 +02:00
fe6eef7069
Windows simulation support
2015-05-09 21:09:52 +08:00
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
c6904f9d63
sim: fix to support ConvOutput
2015-04-12 14:06:57 +08:00
c169f0b189
Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
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This reverts commit f03aa76292
2015-03-30 19:41:16 +08:00
f03aa76292
migen: create VerilogConvert and EDIFConvert classes and return it with convert functions
2015-03-30 11:37:55 +02:00
5f045b7649
sim: keep track of unreferenced items
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* items that are never referenced in any statements do not end up in the
namespace or in the verilog
* this memorizes items if they can not be found in the namespace and keeps
track of their values
2015-03-21 10:02:10 +01:00
dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
0bac463780
sim/icarus: add vpi directory to module search path
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This allows running the iverilog simulations from the migen top directory
without having to install the .vpi anywhere.
2014-09-07 16:49:12 +08:00
9fcea6e64a
migen/sim/generic: use kwargs to pass parameters to icarus.Runner
2014-07-24 10:17:54 -06:00
a36a208dd1
sim: use (mandatory) ncycles when starting a simulation with no active functions
2014-04-13 15:16:27 +02:00
90f0dfad63
Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator
2014-01-27 23:58:46 +01:00
63c1d7e4b7
New simulation API
2014-01-26 22:19:43 +01:00
55afab2276
sim: use Simulator as a contextmanager
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__del__ garbage collector callbacks are too delicate. E.g. imported
modules can be garbage collected before the objects using them. Can't
use os.remove, socket.SHUT_RDWR...
* added a DeprecationWarning if a Simulator is garbage collected without
having its .close() called
* renamed all gc __del__ callbacks to close()
* implemented context manager hooks for Simulator. Use like
with Simulator(TestBench()) as s:
s.run()
2013-11-29 23:05:15 +01:00
b7ed19c6c5
fhdl: do not export Fragment
2013-07-25 18:52:54 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
dd0f3311cd
structure: remove Fragment.call_sim
2013-03-15 19:15:48 +01:00
9b9bd77d00
sim: compatibility with new ClockDomain API
2013-03-15 19:15:28 +01:00
69dbf84e54
sim/generic: support implicit get_fragment
2013-03-12 16:54:01 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
92b67df41c
sim: default runner to Icarus Verilog
2013-02-09 17:04:53 +01:00
50ed73c937
New specification for width and signedness
2012-11-29 21:22:38 +01:00
d2c61e6a90
sim/generic/multiread: do not return spurious items
2012-11-23 23:07:25 +01:00
89643bc434
sim/ipc/Message: convert values
2012-11-17 23:19:40 +01:00
e16353a281
Multi-clock design support + new instance API
2012-09-10 23:45:02 +02:00
6490785b6c
Merge pull request #3 from brandonhamilton/upstream
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Optionally accept iverilog simulator options
2012-09-09 10:52:52 -07:00
5bf19c155f
sim: ensure clean IPC shutdown
2012-08-05 00:16:11 +02:00
8de192dfbd
x.bv.width -> len(x)
2012-07-13 18:32:54 +02:00
8a23451237
PureSimulable
2012-06-12 17:08:56 +02:00
Sebastien Bourdeauducq
Florent Kermarrec
William D. Jones
Robert Jordens
Sebastien Bourdeauducq