Sebastien Bourdeauducq
|
246b860a85
|
csr: new data width API
|
2013-07-28 16:33:36 +02:00 |
|
Sebastien Bourdeauducq
|
70ffe86356
|
New migen.fhdl.std to simplify imports + len->flen
|
2013-05-22 17:11:09 +02:00 |
|
Sebastien Bourdeauducq
|
f9acee4e68
|
corelogic -> genlib
|
2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
4164fb4ac9
|
bus/csr: configurable data width
|
2012-08-26 21:19:34 +02:00 |
|
Sebastien Bourdeauducq
|
e969b9afc3
|
corelogic: convert timeline to function and move to misc
|
2012-03-15 20:25:44 +01:00 |
|
Sebastien Bourdeauducq
|
0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
|
2012-02-15 16:30:16 +01:00 |
|
Sebastien Bourdeauducq
|
8a61d9d121
|
bus/csr: Rename a->adr d->dat to be consistent with the other buses
|
2012-02-13 21:46:39 +01:00 |
|
Sebastien Bourdeauducq
|
47883675db
|
bus/wishbone2csr: truncate WB data
|
2012-02-06 18:43:34 +01:00 |
|
Sebastien Bourdeauducq
|
a99c2acfa8
|
Remove explicit bus names and rely on the new automatic namer
|
2012-01-27 22:20:57 +01:00 |
|
Sebastien Bourdeauducq
|
076c171c7b
|
Use meaningful class names
|
2012-01-20 23:07:32 +01:00 |
|
Sebastien Bourdeauducq
|
20425703fa
|
Wishbone: omit fixed LSBs
|
2012-01-13 17:29:05 +01:00 |
|
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
|
2011-12-16 21:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
|
Sebastien Bourdeauducq
|
929cc98070
|
wishbone2csr: wait for WB deack
|
2011-12-13 17:38:59 +01:00 |
|
Sebastien Bourdeauducq
|
0ea7a9b2e6
|
wishbone2csr: fix double-write bug
|
2011-12-13 00:25:46 +01:00 |
|
Sebastien Bourdeauducq
|
dad9120653
|
bus: 14-bit CSR addresses
|
2011-12-11 20:16:50 +01:00 |
|
Sebastien Bourdeauducq
|
05d91c7104
|
bus: Wishbone to CSR bridge
|
2011-12-11 15:04:34 +01:00 |