330d61d2bd
soc/add_pcie: Remove MSI workaround on Ultrascale(+) now that root cause is understood/fixed (thanks @smunaut).
2023-07-21 14:50:38 +02:00
aae15737cd
CHANGES: Update.
2023-07-20 16:30:48 +02:00
c00f61d9d7
tools: Update to new sdcard core name.
2023-07-20 16:29:05 +02:00
6693a723d1
software: Update to new sdcard core name.
2023-07-20 16:28:51 +02:00
0152e7de8e
soc/add_sata: Use name parameter to allow multiple sdcard instances.
2023-07-20 16:28:22 +02:00
e364316814
soc/add_sata: Use name parameter to allow multiple sata instances.
2023-07-20 16:02:03 +02:00
f995d74e55
soc/add_uartbone: Rename name parameter to uart_name to allow multiple uartbone (also for consistency with other cores) and other minor cleanups.
2023-07-20 15:42:03 +02:00
6e78db6767
soc/add_bus_master: Use name where possible to avoid automatic naming and improve log readability.
2023-07-20 15:15:44 +02:00
f6da67fb38
soc/add_pcie: Add optional data_width parameter.
2023-07-20 10:35:10 +02:00
69c6fa11d2
build/lattice/common/lattice_ecp5_trellis_special_overrides: Add missing DifferentialOutput.
2023-07-17 17:08:35 +02:00
6ab156e225
soc/cores: Fix regressions.
2023-07-17 11:48:39 +02:00
79a82dc732
tools/litex_json2dts_linux: Remove duplicated clock definition.
...
Keep clock definition introduced by 9b67898e99
2023-07-17 11:27:07 +02:00
3d101b9749
integration/export: When csr_base is specified, make CSR regions definition relative to it.
...
Useful for PCIe based systems when internal CSR base is automatically added by the logic.
2023-07-17 11:14:33 +02:00
3fc16f54f1
soc/cores/cpu: Switch to LiteXModule.
2023-07-17 09:26:58 +02:00
39ff69ade7
cores/spi: Switch to LiteXModule.
2023-07-17 09:14:47 +02:00
028f7eb72f
cores/ram: Switch to LiteXModule.
2023-07-17 09:12:25 +02:00
b35c6580e8
soc/cores/clock: Switch to LiteXModule.
2023-07-15 21:54:07 +02:00
8103cf7851
soc/cores: Switch cores to LiteXModule (still need to do cpu, ram, clk, spi).
2023-07-14 22:19:14 +02:00
6e46710678
gen/fhdl/module: Fix CSR clock domain renaming to cores converted to LiteXModule, thanks @smunaut.
2023-07-14 10:01:32 +02:00
987a35e1ec
Merge pull request #1729 from riktw/master
...
Currently using a lite or minimal Vexriscv config with debug and brea…
2023-07-13 15:21:51 +02:00
3a2586c48b
soc/add_pcie: Remove csr_ordering parameter (not useful and remove on litepcie).
2023-07-12 19:42:54 +02:00
f9e32eb3eb
CHANGES: Update.
2023-07-11 16:42:21 +02:00
eb1afbad47
Currently using a lite or minimal Vexriscv config with debug and breakpoints throws an error. Updated the GCC_FLAGS to include these two variants as well.
2023-07-11 16:16:51 +02:00
26732f626f
CHANGES: Update.
2023-07-10 11:24:49 +02:00
d18c6316f4
gen/fhdl/verilog: Improve signal sort by name instead of duid to improve reproducibility.
2023-07-10 11:24:46 +02:00
698b4dd875
Merge pull request #1728 from stone3311/master
...
cores/arm: Fix computed goto in boot helpers
2023-07-10 08:31:07 +02:00
42c422e767
cores/arm: Fix computed goto in boot helpers
2023-07-09 19:16:06 +02:00
e62f51c3eb
gen/genlib/cdc: Add missing import.
2023-07-07 11:51:04 +02:00
2b941cdcd9
gen/genlib: Add copy of genlib.cdc modules that we are using and not supported by Amaranth to prepare #1727 .
2023-07-06 22:23:54 +02:00
e9739b5446
soc: Switch to litex.gen.genlib.misc.
2023-07-06 22:05:23 +02:00
6f98053b1a
litex/gen: Add copy of genlib.misc to prepare for #1727 .
2023-07-06 22:03:41 +02:00
ec43ca77ed
Merge pull request #1724 from stone3311/master
...
cores/zynqmp: Fix boot helper
2023-07-06 09:15:13 +02:00
54f466772b
cores/zynqmp: Fix boot helper
2023-07-05 20:14:05 +02:00
c58f46bb79
CHANGES: Update.
2023-07-03 18:09:56 +02:00
a2d44370bd
CHANGES: Update.
2023-07-03 10:56:29 +02:00
7fa7a4c72a
soc/add_ethernet: Review/Minor changes to TXSlots write-only mode.
2023-07-03 10:50:47 +02:00
646c917d7f
Merge pull request #1720 from sensille/tx_write_only
...
Tx write only
2023-07-03 10:45:52 +02:00
886994aaa4
Merge pull request #1721 from rasmuspeders1/master
...
Make litex_json2renode work with default arty target SOC .json file
2023-06-30 10:05:45 -07:00
26ed13a300
Assume cpu count 1 if not present
2023-06-30 13:46:08 +02:00
8d33dc364f
Only add "cpu PC <opensbi_base>" if opensbi is present
2023-06-30 13:44:31 +02:00
a12703b4ee
litex_json2renode: only add cpu timeProvider if time_provider exists
2023-06-29 14:13:49 +02:00
648c70de82
cmd_litesata: Fix help printf and update CHANGES.
2023-06-28 23:07:17 +02:00
b7cbd6c7fb
Merge pull request #1715 from gsomlo/gls-sata-multisector
...
Update bios for LiteSATA multi-sector read/write changes
2023-06-28 23:03:15 +02:00
74c3ba0992
Merge branch 'enjoy-digital:master' into tx_write_only
2023-06-28 18:56:05 +02:00
2cdc4fb0ab
ci: Use last known working version of Verilator for Microwatt (Thanks @trabucayre).
2023-06-27 14:32:31 +02:00
5524a17702
add tx_write_only flag to add_ethernet
...
This can save some resources in case reading the tx buffer is not needed.
It also makes it easier for synthesis to infer BRAM, tested on Spartan6.
2023-06-27 09:45:50 +02:00
7a7c74faa9
fix radiant bug 'Mal-formed command line - please check for extra quotes in macro' ( #1718 )
...
* fix radiant bug 'Mal-formed command line - please check for extra quotes in macro'
* fix Radiant Mal-formed command line bug (more pythonic)
* (typo, rm line 159) fix Radiant Mal-formed command line bug
---------
Co-authored-by: slagernate@github.com <slagernate@github.com>
2023-06-24 08:57:44 +02:00
8dca488432
software/bios/cmd_litesata: add multisector read/write test
2023-06-22 17:59:18 -04:00
1d2eddbe37
software/bios/cmd_litesata: add multi-sector xfer between SATA and memory
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-06-22 17:59:18 -04:00
7d1e12c870
software/liblitesata: update to multi-sector read, write
...
The LiteSATA gateware now supports multi-sector transfers, and expects
a sector count register to be populated by the software before a DMA
transfer is initiated.
This patch also fixes checks for `done` and `error` during writes by
using the correct `mem2sector` read function (instead of `sector2mem`,
which is for use during read operations).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-06-22 17:59:18 -04:00
Florent Kermarrec
Dolu1990
riktw
stone3311
Gwenhael Goavec-Merou
Tim 'mithro' Ansell
Rasmus Pedersen
Arne Jansen
Nate Slager
Gabriel Somlo