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8791 Commits

Author SHA1 Message Date
enjoy-digital 33fbf558a2
Merge branch 'master' into avalon-burst-test 2023-05-10 11:12:30 +02:00
enjoy-digital 82526460e9
Merge pull request #1684 from hansfbaier/retro-vga 
Add low res video modes
 2023-05-10 11:09:46 +02:00
enjoy-digital 537b1b8530
Merge pull request #1683 from hansfbaier/master 
AvalonMM2Wishbone: use same addressing on avalon and wishbone, leave address translation to the user
 2023-05-10 11:09:13 +02:00
Hans Baier ef904a14e1 AvalonMM2Wishbone: fix burst reads (#1686) 2023-05-10 05:22:49 +07:00
Hans Baier 71a0e398a7 Avalon2Wishbone test: assert readdatavalid on bursts 2023-05-10 04:05:16 +07:00
Hans Baier 90581a2f13 add some low resolution video modes 2023-05-09 15:29:27 +07:00
Hans Baier f00eb4e112 AvalonMM2Wishbone: use same addressing on avalon and wishbone, leave address translation to the user 2023-05-09 15:26:27 +07:00
Florent Kermarrec 3ab7ebe536 CHANGES.md: Release 2023.04. 2023-05-08 10:59:17 +02:00
Florent Kermarrec 3c03b6f5e4 avalon/AvalonMM2Wishbone: Fix avl.readdatavalid. 
Multi-driven, remove assign in BURST-READ.
 2023-05-08 10:18:56 +02:00
Florent Kermarrec dd40c25b23 avalon/AvalonMM2Wishbone: Fix write byteenable/sel. 
From mnl_avalon_spec.pdf:
"The byteenables can change for different words of the burst."
 2023-05-08 10:03:51 +02:00
Florent Kermarrec f7ee9fad96 avalon/AvalonMM2Wishbone: Do other cosmetic changes. 2023-05-08 09:57:35 +02:00
Florent Kermarrec 9f44a498d6 avalon/AvalonMM2Wishbone: Simplify wb.cti. 
In BURST-WRITE/READ, wb.cti can't be BURST_NONE.
 2023-05-08 09:42:12 +02:00
Florent Kermarrec a62149831d avalon/AvalonMM2Wishbone: Avoid reseting burst_set (not useful since always set before use). 2023-05-08 09:29:02 +02:00
Florent Kermarrec 451fb8d378 avalon/AvalonMM2Wishbone: Directly set burst_read in BURST-READ state. 2023-05-08 09:27:05 +02:00
Florent Kermarrec 8e1a3880d3 interconnect/avalon: Switch to directory/python package and split mm/st. 
Similarly to what is done for AXI and will avoid too complex/large files.
 2023-05-08 09:25:16 +02:00
Florent Kermarrec 7071304b10 soc/interconnect/avalon/AvalonMM: Do a first cosmetic cleanup pass. 
- Add separators.
- Use coding style similar to other modules.
- Replace the Mux with simpler If/Else constructs to improve understanding and readability.
 2023-05-08 09:14:35 +02:00
Hans Baier c5c7e86cca
WIP AvalonMM interface and Avalon to Wishbone Bridge (#1674) 
Add initial AvalonMM interface and AvalonMM2Wishbone.
 2023-05-08 08:42:10 +02:00
Florent Kermarrec 85ee31aae7 setup.py: Prepare for 2023.04. 2023-05-07 20:54:04 +02:00
Florent Kermarrec 0f1ad8dcfc CHANGES.md: Update. 2023-05-05 10:08:11 +02:00
Florent Kermarrec f62d380b2f build/yosys_wrapper: Skip language=None files. 2023-05-03 17:33:16 +02:00
Florent Kermarrec 8f26e5f7a8 tools/litex_client: Add binded property to simplify user scripts. 2023-05-03 17:33:12 +02:00
enjoy-digital 34ec22f8ab
Merge pull request #1677 from mntmn/master 
bios/spiflash: fix write/ erase, add write from sdcard and range erase
 2023-04-26 07:11:54 +02:00
Lukas F. Hartmann 1b7d229668 Merge branch 'master' of https://github.com/enjoy-digital/litex 2023-04-25 17:15:44 +02:00
Lukas F. Hartmann e23fe832f0 litespi/flash: fix status reg read; remove delays 2023-04-25 17:05:33 +02:00
Lukas F. Hartmann cb2a789008 bios/spiflash: bring back write and erase, add write from sdcard file cmd 
When shipping MNT RKX7, I pre-flash the SPI flash with a LiteX bitfile
for testing. cmd_spiflash had regressed because of changed SPIFLASH defines
and didn't offer the write functions anymore. This commit fixes that, and
adds convenience functions:

- flash_erase_range <offset> <count (bytes)>
- flash_from_sdcard <filename>

The latter reuses some boot code to copy the contents of the specified
file from the boot FAT partition on the SD card to SPI flash (i.e.
a bitstream).
 2023-04-25 13:30:07 +02:00
Lukas F. Hartmann 118dd6ed08 liblitespi/spiflash: add erase and write functions 
The code is based on norbert thiel's comment https://github.com/litex-hub/litespi/issues/52
But edited to work with W25Q128JVS flash used in MNT RKX7.
 2023-04-25 13:26:18 +02:00
Florent Kermarrec 309f012d2c cores/usb_ohci: Ensure self.usb_clk_freq is an integer (as a workaround to prevent build issue). 2023-04-24 10:31:47 +02:00
Florent Kermarrec b367c27191 integration/soc/zynq: Revert previous commit (incorrect), re-enable CSR decode on Zynq7000/MP and add check/error when SoCBusHandler has more than one Region and one of them has its decoder disabled. 
This will prevent silent errors and means offset needs to be added in Software.
 2023-04-12 19:54:01 +02:00
Florent Kermarrec f44ff2bac4 integration/soc/SoCBusHandler: Force interconnect to Crossbar when at least one region has the decoder disabled. 
See https://github.com/enjoy-digital/litex/issues/1665 since optimizations on Shared Interconnect can't be used with
disabled decoder.
 2023-04-12 19:13:14 +02:00
enjoy-digital cb9f01be9e
Merge pull request #1671 from hansfbaier/master 
give human readable error messages if a connector or pin is not available
 2023-04-11 16:34:46 +02:00
enjoy-digital 748899aa49
Merge pull request #1670 from dasdgw/i2c_fix 
soc/software: fix i2c_write
 2023-04-11 16:34:18 +02:00
Hans Baier 750f8c41b9 distinguish between dict and list connectors in error message 2023-04-11 14:11:48 +07:00
Hans Baier cfaba189c4 give human readable error messages if a connector or pin is not available 2023-04-11 11:09:10 +07:00
dasdgw b1e02ebcfa soc/software: fix i2c_write 
commit 3fa3080e introduced an additional address length paramater to
i2c_write to support non 8bit memory addresses.
But the parameter wasn't added to the call of i2c_write in i2c_send_init_cmds.

This commit fixes the issue by adding the address length parameter to
the call of i2c_write.
 2023-04-10 12:47:15 +02:00
Florent Kermarrec c9e2de21f7 integration/soc: Switch from setattr to add_module. 2023-04-07 09:40:53 +02:00
Florent Kermarrec dc4b748752 integration/soc/add_pcie: Add US(P) specific MSI connection. 
Will preferably have to be understood/fixed directly in the verilog adaptation.
 2023-04-06 18:25:00 +02:00
Florent Kermarrec 0c326f0ed0 cpu/neorv32: Use older commit. 2023-03-30 12:38:27 +02:00
Florent Kermarrec d299957118 cpu/neorv32: Use specific sha1, litex_core_complex will need an update. 2023-03-30 12:06:48 +02:00
Florent Kermarrec ab8d906827 CHANGES.md: Update. 2023-03-30 10:13:56 +02:00
Florent Kermarrec 181d414911 integration/soc/add_pcie: Expose more DMA parameters. 2023-03-27 17:43:03 +02:00
enjoy-digital 4b72dd047e
Merge pull request #1662 from enjoy-digital/multi-channel-pwm 
soc/cores/pwm: Add MultiChannelPWM core reusing PWM module.
 2023-03-24 18:11:55 +01:00
enjoy-digital ffded272d4
Merge pull request #1655 from timkpaine/tkp/distfix 
Small packaging and CI changes
 2023-03-24 18:08:55 +01:00
Florent Kermarrec 4dabf0a330 cpu/vexriscv/naxriscv: Use reserved_interrupts to reserved interrupt 0. 2023-03-24 09:02:49 +01:00
Florent Kermarrec 2d24f50844 soc/add_cpu: Make sure to reserve CPU's reserved interrupt when adding CPU. 2023-03-24 09:02:22 +01:00
Florent Kermarrec e55f0da7c7 software/liblitesdcard: Only use sdcard_stop_transmission when nblocks > 1 (thanks @bayi). 
Similar to what is already done for reads.
 2023-03-24 08:39:50 +01:00
Gabriel Somlo c3e93620ec cpu/rocket: rework variant naming convention 
The naming convention for LiteX Rocket variants has become overly
complex. Simplify it while at the same time adding more flexibility.

There is a new set of instances of varying main RAM memory bus port
width (1x (64bit), 2x (128bit), 4x (256bit), and 8x (512bit)), of
each of the following principal LiteX specific Rocket models:

- small:  (rv64imac, no MMU, no S, no FPU)
- medium: (rv64imac, adds MMU and S-mode)
- linux:  (rv64imafdc, adds FPU, supports linux distros)
- full:   (rv64imafdcbkph[+], adds hypervisor support)

NOTE: before adding H support, the feature set of the old `full`
model is now represented by the `linux` model. The old `linux`
did not use to have an FPU, and is now available as `medium`.

In addition to the range of memory port widths, each model
will be instantiated in 1, 2, 4, and 8 core variants. The
naming convention is `LitexConfig_<model>_<num_cores>_<mem_width>`.

E.g. `LitexConfig_full_8_2` for an 8-core full model with
a 128bit main RAM AXI port. On the build command line, this
example would look like:

	...
	--cpu-type rocket --cpu-variant full \
	--cpu-num-cores 8 --cpu-mem-width 2 \
	...

There are a total of 4 * 4 * 4 = 64 (sub-)variants: each of the four
principal models can be fitted with one of four core counts, and one
of four memory bus widths.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2023-03-22 12:26:03 -04:00
Florent Kermarrec 5e5b929ee6 soc/cores/pwm: Add MultiChannelPWM core reusing PWM module. 
Also do minor changes to PWM module to allow reuse.
 2023-03-22 14:52:38 +01:00
enjoy-digital 1c43a71970
Merge pull request #1636 from gatecat/cva6_rv32 
CVA6: Adding RV32 support
 2023-03-22 12:06:52 +01:00
enjoy-digital 6274b0e9bf
Merge branch 'master' into cva6_rv32 2023-03-22 09:30:03 +01:00
enjoy-digital 6b362969e8
Merge pull request #1654 from shenki/rocket-cva6-csr 
cpu: rocket, cva6: Fix compilation with newer binutils
 2023-03-22 09:27:49 +01:00