Sebastien Bourdeauducq
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3be20f6ae4
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dfii: adapt to new Record API
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2013-04-02 00:15:42 +02:00 |
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Sebastien Bourdeauducq
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4f4f260e76
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Convert to new CSR API
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2013-03-30 17:28:15 +01:00 |
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Sebastien Bourdeauducq
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caa19f9ab2
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framebuffer: larger counters
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2013-03-29 17:15:11 +01:00 |
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Sebastien Bourdeauducq
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854c0461b4
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framebuffer: process two pixels per system clock cycle
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2013-03-28 20:46:16 +01:00 |
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Sebastien Bourdeauducq
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8fd092ca12
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crg: support VGA pixel clock reprogramming
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2013-03-28 19:07:17 +01:00 |
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Sebastien Bourdeauducq
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1e860c7472
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Use new Mibuild generic_platform API
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2013-03-26 17:57:17 +01:00 |
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Sebastien Bourdeauducq
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1045d64e6e
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framebuffer: RGBA -> ARGB
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2013-03-25 18:32:25 +01:00 |
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Sebastien Bourdeauducq
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8ee6dab4f9
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fb: better ordering of pixels within ASMI words
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2013-03-25 15:56:54 +01:00 |
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Sebastien Bourdeauducq
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1333367de8
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dvisampler: add resolution detection
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2013-03-24 00:45:29 +01:00 |
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Sebastien Bourdeauducq
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ee5bfd4d3d
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dvisampler/charsync: report position
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2013-03-24 00:44:50 +01:00 |
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Sebastien Bourdeauducq
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99f9ffa7e8
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dvisampler/decoding: set C to 0 during data
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2013-03-24 00:44:19 +01:00 |
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Sebastien Bourdeauducq
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fb9a2788e8
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dvisampler/charsync: fix found_control signal
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2013-03-24 00:43:22 +01:00 |
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Sebastien Bourdeauducq
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e06585d9fe
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dvisampler: clean up EDID data
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2013-03-23 13:48:40 +01:00 |
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Sebastien Bourdeauducq
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34b8388b45
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dvisampler: decode before channel sync
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2013-03-22 23:49:25 +01:00 |
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Sebastien Bourdeauducq
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037625886d
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dvisampler: decoding
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2013-03-22 21:28:17 +01:00 |
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Sebastien Bourdeauducq
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d65941d6cc
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dvisampler: channel synchronization
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2013-03-22 18:37:10 +01:00 |
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Sebastien Bourdeauducq
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515cdb2bd8
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dvisampler: character synchronization
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2013-03-21 22:56:13 +01:00 |
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Sebastien Bourdeauducq
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7c4ca4fd66
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dvisampler/datacapture: deserialize to 10 bits
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2013-03-21 19:06:15 +01:00 |
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Sebastien Bourdeauducq
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fa2331e084
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dvisampler/clocking: generate pix reset
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2013-03-21 19:02:04 +01:00 |
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Sebastien Bourdeauducq
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0a14c3714b
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dvisampler: software controlled phase detector
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2013-03-21 00:46:29 +01:00 |
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Sebastien Bourdeauducq
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28cb97068c
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dvisampler/clocking: proper pix5x reset synchronization
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2013-03-18 20:31:59 +01:00 |
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Sebastien Bourdeauducq
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5126f616fb
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dvisampler: use pix5x as IODELAY clock
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2013-03-18 19:03:17 +01:00 |
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Sebastien Bourdeauducq
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48aae9bee5
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Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
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2013-03-18 17:44:01 +01:00 |
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Sebastien Bourdeauducq
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74cc045ee1
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dvisampler/datacapture: connect IODELAY IOCLK0
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2013-03-17 17:42:22 +01:00 |
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Sebastien Bourdeauducq
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621526fb7d
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dvisampler/datacapture: fix tap counter reg
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2013-03-17 17:36:49 +01:00 |
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Sebastien Bourdeauducq
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3a0cf278fd
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dvisampler: fixes
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2013-03-17 15:41:50 +01:00 |
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Sebastien Bourdeauducq
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9f02ced39e
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dvisampler: add clocking and phase detector
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2013-03-17 14:43:10 +01:00 |
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Sebastien Bourdeauducq
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0168f83523
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MultiReg: remove idomain
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2013-03-15 19:51:29 +01:00 |
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Sebastien Bourdeauducq
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b2173bba9f
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Use new ClockDomain API
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2013-03-15 19:17:05 +01:00 |
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Sebastien Bourdeauducq
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e99bafe52b
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dvisampler: add core, EDID support
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2013-03-13 19:56:26 +01:00 |
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Sebastien Bourdeauducq
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a23df42a7a
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Use automatic register naming
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2013-03-12 15:47:54 +01:00 |
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Sebastien Bourdeauducq
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a9b723568a
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Use new module, autoreg and eventmanager Migen APIs
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2013-03-10 19:32:38 +01:00 |
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Sebastien Bourdeauducq
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0caac2246d
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Use new 'specials' API
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2013-02-24 13:07:25 +01:00 |
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Sebastien Bourdeauducq
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a22ada36d7
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corelogic -> genlib
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2013-02-24 12:31:00 +01:00 |
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Sebastien Bourdeauducq
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5649e88a90
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Use Mibuild
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2013-02-11 18:23:06 +01:00 |
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Sebastien Bourdeauducq
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51f4f920a2
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Do not use super()
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2012-12-18 14:55:58 +01:00 |
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Sebastien Bourdeauducq
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c44ff8941c
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Move Token
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2012-12-14 15:54:16 +01:00 |
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Sebastien Bourdeauducq
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3986790621
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Remove ActorNode
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2012-12-12 22:52:55 +01:00 |
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Sebastien Bourdeauducq
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053f8ed82c
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Fix instantiations
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2012-12-06 20:57:00 +01:00 |
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Sebastien Bourdeauducq
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fee70e9866
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Use Wishbone SRAM component from Migen
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2012-12-01 12:59:32 +01:00 |
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Sebastien Bourdeauducq
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293a62dabe
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Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 23:41:51 +01:00 |
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Sebastien Bourdeauducq
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8bf6945dfd
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Use new bitwidth/signedness system
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2012-11-29 23:38:04 +01:00 |
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Sebastien Bourdeauducq
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7e2bc00c0a
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Remove Constant
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2012-11-28 23:18:53 +01:00 |
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Sebastien Bourdeauducq
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79e5f24a65
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Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.
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2012-11-28 22:49:22 +01:00 |
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Sebastien Bourdeauducq
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0620e75cb8
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sram: do not use MemoryPort
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2012-11-26 19:32:56 +01:00 |
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Sebastien Bourdeauducq
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ced98d7bee
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framebuffer: use new SingleGenerator
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2012-10-09 21:11:26 +02:00 |
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Sebastien Bourdeauducq
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dd6eacba62
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Remove uses of the RE signal on field registers
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2012-10-09 19:08:37 +02:00 |
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Sebastien Bourdeauducq
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c86dd3cbef
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Define clock domains instead of passing extra clocks as regular signals
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2012-09-11 00:21:07 +02:00 |
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Sebastien Bourdeauducq
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5931c5eb59
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Basic support for new clock domain and instance API
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2012-09-10 23:47:06 +02:00 |
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Sebastien Bourdeauducq
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42d5e850fe
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framebuffer: disable debugger by default
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2012-08-05 01:11:37 +02:00 |