Sebastien Bourdeauducq
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45797f9132
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framebuffer: saturate instead of overflow
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2013-05-16 17:45:21 +02:00 |
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Sebastien Bourdeauducq
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a39bf8ca7b
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software/videomixer: support additive blending (enable with SW1, status on LED)
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2013-05-16 17:44:49 +02:00 |
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Sebastien Bourdeauducq
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ac64701e19
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software/videomixer: better pot calibration
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2013-05-16 17:43:56 +02:00 |
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Sebastien Bourdeauducq
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71cc2db867
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Add GPIO buttons and LEDs
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2013-05-16 17:43:20 +02:00 |
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Sebastien Bourdeauducq
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581cf5bcb8
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timer: atomic reads
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2013-05-13 17:18:30 +02:00 |
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Sebastien Bourdeauducq
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9f81afb844
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software/videomixer: connect crossfade and blackout pots
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2013-05-13 15:45:28 +02:00 |
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Sebastien Bourdeauducq
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32c478af16
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top: integrate ADC for pots
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2013-05-13 15:45:06 +02:00 |
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Sébastien Bourdeauducq
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6bf6477dbc
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Merge pull request #1 from fallen/makefile-001
Some Makefile love
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2013-05-13 00:38:26 -07:00 |
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Sebastien Bourdeauducq
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bb73558ccc
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software/videomixer: framebuffer enable/disable
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2013-05-12 21:46:16 +02:00 |
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Sebastien Bourdeauducq
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534dec62eb
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First video mixing working (hacky)
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2013-05-12 15:58:08 +02:00 |
Yann Sionneau
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301008cd0c
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Some Makefile love
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2013-05-12 14:24:18 +02:00 |
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Sebastien Bourdeauducq
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e35315bb24
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cleanup
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2013-05-11 12:45:30 +02:00 |
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Sebastien Bourdeauducq
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8c335d66fd
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framebuffer: fix alpha blending
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2013-05-11 09:21:12 +02:00 |
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Sebastien Bourdeauducq
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e96b027dee
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Framebuffer mixing
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2013-05-10 21:03:55 +02:00 |
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Sebastien Bourdeauducq
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3ab83fb693
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framebuffer: reorganize in preparation for mixer
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2013-05-09 19:23:22 +02:00 |
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Sebastien Bourdeauducq
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6f11ddb079
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software/dvisampler: periodically reset PLL until locked + recalibrate IO every second
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2013-05-09 14:11:08 +02:00 |
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Sebastien Bourdeauducq
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546aa76aef
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software/dvimixer: support two channels
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2013-05-09 13:41:21 +02:00 |
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Sebastien Bourdeauducq
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06064d33aa
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dvisampler/dma: better 8:8:8 -> 10:10:10 conversion
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2013-05-09 11:27:24 +02:00 |
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Sebastien Bourdeauducq
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c6d553e4e4
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software/videomixer: interrupt-driven video passthrough
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2013-05-09 10:52:43 +02:00 |
|
Sebastien Bourdeauducq
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fe87221d2b
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dvisampler/dma: reverse slot allocation order
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2013-05-09 10:51:50 +02:00 |
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Sebastien Bourdeauducq
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2df4ff0ad9
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dvisampler/dma: fix interrupt generation
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2013-05-09 10:51:34 +02:00 |
|
Sebastien Bourdeauducq
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d685ed21fc
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dvisampler/dma: bugfixes
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2013-05-08 22:50:40 +02:00 |
|
Sebastien Bourdeauducq
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66b4bae7c8
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top: connect dvisampler DMA IRQs
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2013-05-08 22:31:42 +02:00 |
|
Sebastien Bourdeauducq
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b3d87e1c79
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software/videomixer: use new DMA engine
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2013-05-08 22:31:18 +02:00 |
|
Sebastien Bourdeauducq
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29efa85dec
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dvisampler: new DMA engine (buggy)
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2013-05-08 22:31:01 +02:00 |
|
Sebastien Bourdeauducq
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89dbc37ece
|
cif: do not generate write function for CSRStatus
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2013-05-08 20:58:27 +02:00 |
|
Sebastien Bourdeauducq
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8e76c960d9
|
timer, uart: EventSourceLevel -> EventSourceProcess
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2013-05-08 18:11:42 +02:00 |
|
Sebastien Bourdeauducq
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e2d15b169a
|
dvisampler: mostly working, very basic and slightly buggy DMA
|
2013-05-06 09:58:12 +02:00 |
|
Sebastien Bourdeauducq
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f82a16f3a3
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software/videomixer: send to framebuffer
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2013-05-06 09:56:49 +02:00 |
|
Sebastien Bourdeauducq
|
679d13c99c
|
another attempt at fixing clock routing issues
|
2013-05-06 09:56:10 +02:00 |
|
Sebastien Bourdeauducq
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784e96bb87
|
build.py: LOC clock generator components to limit breakage of the ISE shitware
|
2013-05-05 23:07:15 +02:00 |
|
Sebastien Bourdeauducq
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11cbdf0d4f
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build.py: support single DVI sampler
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2013-05-05 20:56:58 +02:00 |
|
Sebastien Bourdeauducq
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d05f3d22e0
|
chansync: bugfix
|
2013-05-05 15:07:57 +02:00 |
|
Sebastien Bourdeauducq
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9c0d13b615
|
tb: add chansync
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2013-05-05 15:07:36 +02:00 |
|
Sebastien Bourdeauducq
|
d175e01876
|
dvisampler: connect sync polarity detection
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2013-05-05 12:58:53 +02:00 |
|
Sebastien Bourdeauducq
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cb008a061c
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dvisampler/chansync: fix FIFO width
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2013-05-05 12:58:24 +02:00 |
|
Sebastien Bourdeauducq
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ad01dc8a74
|
software/videomixer: use new resdetection regs
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2013-05-05 11:58:43 +02:00 |
|
Sebastien Bourdeauducq
|
ea20b74ed1
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dvisampler/resdetection: use DE instead of hsync
|
2013-05-05 11:54:36 +02:00 |
|
Sebastien Bourdeauducq
|
e3e1dcd547
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dvisampler: add sync polarity detection module (thanks Lars for suggestions)
|
2013-05-05 11:53:38 +02:00 |
|
Sebastien Bourdeauducq
|
71e3bba228
|
dvisampler/decoding: hold C when DE=1
|
2013-05-05 11:51:48 +02:00 |
|
Sebastien Bourdeauducq
|
4259699d78
|
dvisampler: add RawDVISampler
|
2013-05-04 20:40:21 +02:00 |
|
Sebastien Bourdeauducq
|
63073319b0
|
dvisampler/datacapture: swap bit pairs
|
2013-05-04 20:38:50 +02:00 |
|
Sebastien Bourdeauducq
|
53e5c4f59c
|
build: only add UCF constraints for the cores that are present
|
2013-05-02 23:56:09 +02:00 |
|
Sebastien Bourdeauducq
|
26c0261a4e
|
Remove unneeded file
|
2013-05-01 17:13:40 +02:00 |
|
Sebastien Bourdeauducq
|
2e3c2611a6
|
software: put network code in a library
|
2013-05-01 00:12:13 +02:00 |
|
Sebastien Bourdeauducq
|
8222ee7f46
|
framebuffer: use DMA controller from Migen
|
2013-04-30 18:55:35 +02:00 |
|
Sebastien Bourdeauducq
|
43ac5c8471
|
Remove undriven reset signals
|
2013-04-25 20:19:49 +02:00 |
|
Sebastien Bourdeauducq
|
de76faf757
|
Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark.
|
2013-04-25 20:18:45 +02:00 |
|
Sebastien Bourdeauducq
|
4ff1175dcf
|
Use the Migen asynchronous FIFO
|
2013-04-25 19:43:26 +02:00 |
|
Sebastien Bourdeauducq
|
d64b64501a
|
minimac3: move psync
|
2013-04-25 18:36:45 +02:00 |