Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
7,096 Commits 40 Branches 14 Tags 51 MiB
Commit Graph

7096 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 8f1bf508ca actor: simplified automatic control 2012-01-06 15:35:17 +01:00
Sebastien Bourdeauducq a3bf877802 ALA: use records for tokens 2012-01-06 14:32:00 +01:00
Sebastien Bourdeauducq 1905eb3707 README: update copyright year 2012-01-06 14:15:57 +01:00
Sebastien Bourdeauducq 038992e7d2 corelogic: record 2012-01-06 11:20:44 +01:00
Sebastien Bourdeauducq d7a3bed44c Signal repr 2012-01-06 11:20:33 +01:00
Sebastien Bourdeauducq 4c040810bc Merge branch 'master' of github.com:milkymist/migen 2012-01-05 19:27:55 +01:00
Sebastien Bourdeauducq b60abfaa4a Convert -> convert 2012-01-05 19:27:45 +01:00
Sebastien Bourdeauducq 9366a226bb Convert -> convert 2012-01-05 19:27:33 +01:00
Alain Péteut 6bd8566c48 setup.py: fix to catch all modules 
Signed-off-by: Alain Péteut <peteut@space.unibe.ch>
 2011-12-27 11:19:37 +01:00
Alain Péteut 5f53e6473a Add setup script 2011-12-24 13:46:40 +01:00
Sebastien Bourdeauducq 1ce4fbdb98 example: flow conversion 2011-12-23 00:36:07 +01:00
Sebastien Bourdeauducq edf90870c2 flow: sum and division actors 2011-12-23 00:35:53 +01:00
Sebastien Bourdeauducq 76db20cd9f fhdl: encapsulate replicated constants 2011-12-23 00:35:13 +01:00
Sebastien Bourdeauducq f0aac4b50f flow: actor class 2011-12-22 19:37:16 +01:00
Sebastien Bourdeauducq 566295dea3 csr: use optree 2011-12-22 19:36:56 +01:00
Sebastien Bourdeauducq ba40f58491 corelogic: operator tree 2011-12-22 15:46:19 +01:00
Sebastien Bourdeauducq 8a394f9159 verilog: comb reset 2011-12-22 00:04:53 +01:00
Sebastien Bourdeauducq 4d6be55e9f verilog: break down Convert function 2011-12-21 23:08:50 +01:00
Sebastien Bourdeauducq 26e0b817e8 verilog: ignore variable property in combinatorial block 2011-12-21 23:00:36 +01:00
Sebastien Bourdeauducq 7456195775 Consistent names 2011-12-21 22:57:07 +01:00
Sebastien Bourdeauducq 47d321cd75 README: Flow 2011-12-20 00:07:46 +01:00
Sebastien Bourdeauducq d9dc604c99 README: Core Logic, Bus, Bank 2011-12-19 23:24:31 +01:00
Sebastien Bourdeauducq 7774ace7e1 README: structure + FHDL description 2011-12-19 22:15:10 +01:00
Sebastien Bourdeauducq 3b640c45bb Use new syntax 2011-12-18 22:02:05 +01:00
Sebastien Bourdeauducq af0a03b65f examples: remove old-style declarations 2011-12-18 21:54:39 +01:00
Sebastien Bourdeauducq 94c5fba067 corelogic: fix signal exports 2011-12-18 21:54:28 +01:00
Sebastien Bourdeauducq 4f4d809a4e fhdl: better matching of assignment 2011-12-18 21:49:48 +01:00
Sebastien Bourdeauducq 107f03fd4b Remove uses of declare_signal 2011-12-18 21:47:48 +01:00
Sebastien Bourdeauducq dd42b2daff fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal 2011-12-18 21:47:29 +01:00
Sebastien Bourdeauducq 41e2430e2b fhdl: automatic signal name from assignment 2011-12-18 21:26:51 +01:00
Sebastien Bourdeauducq 6664af73d1 uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
Sebastien Bourdeauducq 135a2eb868 bank: support raw registers 2011-12-18 00:28:04 +01:00
Sebastien Bourdeauducq d21e095397 fhdl: fix series of if/elif/else 2011-12-17 20:31:42 +01:00
Sebastien Bourdeauducq 1a845d4553 32-device, 8-bit CSR bus 2011-12-17 15:54:49 +01:00
Sebastien Bourdeauducq bb21f7584a 32-device, 8-bit CSR bus 2011-12-17 15:54:42 +01:00
Sebastien Bourdeauducq 1b3edd07ca norflash tb: use get_fragment 2011-12-17 15:22:26 +01:00
Sebastien Bourdeauducq 6f8a6db40a verilog: get the simulator to run the combinatorial process at the beginning 2011-12-17 15:20:22 +01:00
Sebastien Bourdeauducq 0e30d67fa3 Multiply system clock 2011-12-17 15:00:18 +01:00
Sebastien Bourdeauducq 85fbe07b94 clkfx module 2011-12-17 15:00:11 +01:00
Sebastien Bourdeauducq ec47394012 verilog: support for float parameters in instances 2011-12-17 14:59:27 +01:00
Sebastien Bourdeauducq 411e1af980 Proper reset generation 2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq ee6ca729a2 verilog: user-definable reset and clock 2011-12-16 22:25:05 +01:00
Sebastien Bourdeauducq 738b45dcbd Support the new FHDL syntax 2011-12-16 21:30:22 +01:00
Sebastien Bourdeauducq c7b9dfc203 fhdl: simpler syntax 2011-12-16 21:30:14 +01:00
Sebastien Bourdeauducq 39b7190334 Pay a bit more attention to PEP8 2011-12-16 16:02:55 +01:00
Sebastien Bourdeauducq ca68097ef6 Pay a bit more attention to PEP8 2011-12-16 16:02:49 +01:00
Sebastien Bourdeauducq 929cc98070 wishbone2csr: wait for WB deack 2011-12-13 17:38:59 +01:00
Sebastien Bourdeauducq b487e99bcf Initial import 2011-12-13 17:33:12 +01:00
Sebastien Bourdeauducq 22d03b4943 timeline: only trigger in rest state 2011-12-13 15:25:46 +01:00
Sebastien Bourdeauducq 6f7a35e0a3 examples: Wishbone interconnect test bench 2011-12-13 14:10:56 +01:00