10495e72d0
lm32: rename mem array in lm32_dp_ram
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Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:06 +01:00
47baad4fe1
lm32: replace clogb2 by builtin $clog2
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This function is fixed in ISE since version 14.1 (see AR #44586 ). If the
builtin function is used, the design can be simulated with Icarus Verilog.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:07:28 +01:00
bf5ce8dc20
pytholite: move expression and register handling to separate modules
2012-11-11 23:48:23 +01:00
f59fd69e34
pytholite/compiler: recognize composite I/O pattern
2012-11-11 18:03:16 +01:00
0b5652bb79
pytholite/compiler: visit_assign_special
2012-11-11 15:52:06 +01:00
687d18a150
pytholite: move FSM management to separate module
2012-11-11 14:30:25 +01:00
409a5570e4
pytholite/compiler: refactor visit_block
2012-11-11 14:17:52 +01:00
fb63698ef4
pytholite/compiler: clean up visit_statement
2012-11-10 23:30:14 +01:00
6ebd1e4503
pytholite: forward 'yield call' statements to io module
2012-11-10 22:59:14 +01:00
48acb1bcfd
pytholite: introduce io module
2012-11-10 21:51:19 +01:00
6776f06a42
pytholite/compiler: support bitslice
2012-11-10 18:04:05 +01:00
37f113c3ea
pytholite/compiler: support range(constants) in for loops
2012-11-10 15:26:13 +01:00
370bab1190
pytholite/compiler: cleanup print statements
2012-11-10 15:10:57 +01:00
39c7dc7d63
pytholite/compiler: support for loops (iterating on lists only)
2012-11-10 15:02:55 +01:00
93db3edd00
pytholite/compiler: support while loops
2012-11-10 14:37:33 +01:00
a901ef46ab
Revert "pytholite/compiler: SymbolStack"
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This reverts commit f57da497b2
2012-11-10 12:09:45 +01:00
f57da497b2
pytholite/compiler: SymbolStack
2012-11-09 23:02:16 +01:00
5750c7c07e
pytholite/compiler: improve naming of selection signals
2012-11-09 20:19:22 +01:00
4921a34616
pytholite/compiler: fix handling of constants
2012-11-09 20:17:57 +01:00
26cf1b8840
fhdl: make constants hashable
2012-11-09 20:17:43 +01:00
c1b8492b61
pytholite/compiler: go to next state
2012-11-09 20:12:15 +01:00
e1075a962c
pytholite/compiler: support if statements
2012-11-09 19:37:52 +01:00
92ff5095da
pytholite/compiler: support comparisons in expressions
2012-11-09 18:41:32 +01:00
a645e0b24e
pytholite/compiler: create FSM
2012-11-09 17:37:42 +01:00
7744655ef2
fhdl/visit: add missing self
2012-11-09 17:37:24 +01:00
13af0ce556
fhdl: visit module (untested)
2012-11-09 16:00:11 +01:00
9c182c47d1
pytholith: add register muxes
2012-11-08 21:49:20 +01:00
18758d87f6
pytholite: do not use ast.NodeVisitor
2012-11-06 13:52:19 +01:00
56d4cdeb48
fhdl/structure: make all values hashable
2012-11-06 13:51:51 +01:00
3042f047fe
pytholite: visit AST and list registers
2012-10-31 15:59:12 +01:00
b171b3b3c2
pytholite: transformable elements
2012-10-29 18:13:03 +01:00
31cdb02eff
bank/description: regprefix
2012-10-15 21:21:59 +02:00
7a1a781f49
actorlib/spi: typo
2012-10-15 21:21:42 +02:00
daee4fb58c
transform/unroll_sync: autodetect in/out
2012-10-15 20:32:07 +02:00
fecab5518b
transform/unroll_sync: support generator function
2012-10-15 19:42:30 +02:00
9efc581bee
transform/unroll: support empty dictionaries
2012-10-12 21:54:48 +02:00
eacba52fba
transform/unroll: support for variables
2012-10-12 19:54:03 +02:00
e5fc9cc675
transform: unroll
2012-10-12 13:16:39 +02:00
ced98d7bee
framebuffer: use new SingleGenerator
2012-10-09 21:11:26 +02:00
d329d40fe9
actorlib/spi: SingleGenerator
2012-10-09 21:11:15 +02:00
dd6eacba62
Remove uses of the RE signal on field registers
2012-10-09 19:08:37 +02:00
c473718a12
actorlib/spi/collector: atomic update for write_count
2012-10-09 19:08:09 +02:00
85081793cf
bank: remove RE signal for field registers
2012-10-09 19:07:53 +02:00
e410973352
bank: support for atomic writes
2012-10-08 18:43:18 +02:00
24877f271b
actorlib/spi: fix memory port we/wd
2012-10-04 20:10:24 +02:00
035870703f
flow/actorlib: Simple Processor Interface (WIP)
2012-10-04 18:22:22 +02:00
8101b68965
fhdl: fix instance get_io
2012-09-28 18:02:03 +02:00
f96a28fc32
start MigLa Doc
2012-09-26 23:05:38 +02:00
c273866b08
fhdl: support expressions in instance ports
2012-09-22 20:51:10 +02:00
2fc9cae88a
fhdl: support inverted clock ports in instances
2012-09-22 20:50:49 +02:00
Michael Walle
Sebastien Bourdeauducq
Florent Kermarrec