Currently the code uses the SoC bus width to calculate the alignment of
CSR banks.
However when we get AXI-Lite interconnect support, the CSR bus is not
directly converted from SoC bus now, instead an intermediate bus with
default parameter (which means 32-bit) is created, CSR bus is converted
from it, and finally this bus is attached to the main interconnect with
auto converter if needed. In this case the intermediate bus is always of
32 bit bus width, eliminating the need of caring the SoC bus width when
handling CSR banks.
Tested on 64-bit SoC bus width now; to make the bus further wider,
other codes need to be changed either.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Currently L1$ flush code does not work well because of lack of
synchorizing.
Switch to use T-Head extended instructions instead of CSRs to flush L1
cache (both D and I), and THEADISAEE is set for this.
In addition, Some other performance-related options are enabled too,
including branch predicting, cache prefetching, etc.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Defines WITH_CXX to the C compiler when including hello.cpp in the demo.
This fixes a bug wahere the the menu did not include the hellocpp item
even when --with-cpp was passed to demo.py
Signed-off-by: Alan Green <alan.green@gmail.com>
We made the bus width of C906 wrong at first, and when we convert its
external interface from AXI-Lite to AXI, it's id width is wrong too.
In addition, the AXI down converter of LiteX is quite weird, so a AXI2WB
bridge is integrated into the core now, like what is done in CVA6.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
The csr opcodes are no longer part of the i instruction set, and must be
enabled separately. This can be done by adding _zicsr to the march
string, eg. -march=rv32i_zicsr. However this is not recognised by older
toolchains, so we can't change over until everyone is using binutils
2.28 or later.
An alternate fix was merged for Vexriscv by patching .S files in
https://github.com/enjoy-digital/litex/pull/1292. This only fixes the
problem for .S files, so the usage of csr instructions in c files was
still broken.
Later it was fixed for all source files for Vexriscv in
https://github.com/enjoy-digital/litex/pull/1321 by telling the compiler
to target the 2.0 ISA, where the csr instructions were still present.
Make the same change to all riscv cpus that specify -march=rv32. This
should allow both old and new toolchains to build software.
Signed-off-by: Joel Stanley <joel@jms.id.au>
As of April 2022, GHDL can output Verilog directly without the use of
yosys. This simplifies the build environment for flows that simply want
to convert VHDL to Verilog.
Note that this removes some arguments from ghdl that are not required to
synthesise ether Microwatt or neorv32.
Signed-off-by: Joel Stanley <joel@jms.id.au>
CSRs added to the Main Module were silently ignored. These are now collected and automatically
added to a "main" Sub-Module.
This feature is useful to quickly create/add CSRs in the design when debugging, ex:
# Adds a "debug" CSR to a SoC and connect register to pads:
self.debug = CSRStorage()
self.comb += pads.debug.eq(self.debug.storage).
LiteXModule can be used as a remplacement of Migen's Module and in this initial version:
- Automatically inherit from AutoCSR (Forgeting to inherit from AutoCSR on a Module was a common mistake).
- Simplify design creation with:
- m.module_x = .. equivalent of Migen's m.submodules.module_x = ..
- m.special_x = .. equivalent of Migen's m.specials.special_x = ..
- m.cd_x = .. equivalent of Migen's m.clock_domains.cd_x = ..
- m += module_x equivalent of Migen's m.submodules += module_x.
- m += special_x equivalent of Migen's m.specials += special_x.
- m += cd_x equivalent of Migen's m.clock_domains += cd_x.
-> Forgeting to attach a correctly a Sub-module/Special was a very common mistake and having to use
m.submodules., m.specials., m.clock_domains. was not natural.
Florent Kermarrec
Icenowy Zheng
Christian Klarhorst
Alan Green
Joel Stanley
Gwenhael Goavec-Merou
Tim 'mithro' Ansell